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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2009-08-02 18:27:36 +0000 |
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| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2009-08-02 18:27:36 +0000 |
| commit | 26a84d4f3c9f7bf88678dd7574261ec66c4f8952 (patch) | |
| tree | 27286ca3495e4fa6ba1a0485fe4036fcd08b4c1c /lib/Target/Blackfin/README.txt | |
| parent | 63cc527fbce3d1e4b47b687c404b1777fa15ffe5 (diff) | |
| download | external_llvm-26a84d4f3c9f7bf88678dd7574261ec66c4f8952.zip external_llvm-26a84d4f3c9f7bf88678dd7574261ec66c4f8952.tar.gz external_llvm-26a84d4f3c9f7bf88678dd7574261ec66c4f8952.tar.bz2 | |
Add support for CPU features (i.e., bugs) and workarounds.
This is just the framework to identify the needed workarounds. They are not actually implemented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77902 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Blackfin/README.txt')
| -rw-r--r-- | lib/Target/Blackfin/README.txt | 72 |
1 files changed, 72 insertions, 0 deletions
diff --git a/lib/Target/Blackfin/README.txt b/lib/Target/Blackfin/README.txt index 67c1e51..b4c8227 100644 --- a/lib/Target/Blackfin/README.txt +++ b/lib/Target/Blackfin/README.txt @@ -170,3 +170,75 @@ Stores: | I-- | * | | * | * | | | I++M | * | | | | | +* Workarounds and features +Blackfin CPUs have bugs. Each model comes in a number of silicon revisions with +different bugs. We learn about the CPU model from the -mcpu switch. + +** Interpretation of -mcpu value +- -mcpu=bf527 refers to the latest known BF527 revision +- -mcpu=bf527-0.2 refers to silicon rev. 0.2 +- -mcpu=bf527-any refers to all known revisions +- -mcpu=bf527-none disables all workarounds + +The -mcpu setting affects the __SILICON_REVISION__ macro and enabled workarounds: + +| -mcpu | __SILICON_REVISION__ | Workarounds | +|------------+----------------------+--------------------| +| bf527 | Def Latest | Specific to latest | +| bf527-1.3 | Def 0x0103 | Specific to 1.3 | +| bf527-any | Def 0xffff | All bf527-x.y | +| bf527-none | Undefined | None | + +These are the known cores and revisions: + +| Core | Silicon | Processors | +|-------------+--------------------+-------------------------| +| Edinburgh | 0.3, 0.4, 0.5, 0.6 | BF531 BF532 BF533 | +| Braemar | 0.2, 0.3 | BF534 BF536 BF537 | +| Stirling | 0.3, 0.4, 0.5 | BF538 BF539 | +| Moab | 0.0, 0.1, 0.2 | BF542 BF544 BF548 BF549 | +| Teton | 0.3, 0.5 | BF561 | +| Kookaburra | 0.0, 0.1, 0.2 | BF523 BF525 BF527 | +| Mockingbird | 0.0, 0.1 | BF522 BF524 BF526 | +| Brodie | 0.0, 0.1 | BF512 BF514 BF516 BF518 | + + +** Compiler implemented workarounds +Most workarounds are implemented in header files and source code using the +__ADSPBF527__ macros. A few workarounds require compiler support. + +| Anomaly | Macro | GCC Switch | +|----------+--------------------------------+------------------| +| Any | __WORKAROUNDS_ENABLED | | +| 05000074 | WA_05000074 | | +| 05000244 | __WORKAROUND_SPECULATIVE_SYNCS | -mcsync-anomaly | +| 05000245 | __WORKAROUND_SPECULATIVE_LOADS | -mspecld-anomaly | +| 05000257 | WA_05000257 | | +| 05000283 | WA_05000283 | | +| 05000312 | WA_LOAD_LCREGS | | +| 05000315 | WA_05000315 | | +| 05000371 | __WORKAROUND_RETS | | +| 05000426 | __WORKAROUND_INDIRECT_CALLS | Not -micplb | + +** GCC feature switches +| Switch | Description | +|---------------------------+----------------------------------------| +| -msim | Use simulator runtime | +| -momit-leaf-frame-pointer | Omit frame pointer for leaf functions | +| -mlow64k | | +| -mcsync-anomaly | | +| -mspecld-anomaly | | +| -mid-shared-library | | +| -mleaf-id-shared-library | | +| -mshared-library-id= | | +| -msep-data | Enable separate data segment | +| -mlong-calls | Use indirect calls | +| -mfast-fp | | +| -mfdpic | | +| -minline-plt | | +| -mstack-check-l1 | Do stack checking in L1 scratch memory | +| -mmulticore | Enable multicore support | +| -mcorea | Build for Core A | +| -mcoreb | Build for Core B | +| -msdram | Build for SDRAM | +| -micplb | Assume ICPLBs are enabled at runtime. | |