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| author | Stephen Hines <srhines@google.com> | 2013-01-21 13:15:17 -0800 |
|---|---|---|
| committer | Stephen Hines <srhines@google.com> | 2013-01-21 13:15:17 -0800 |
| commit | 059800f9e3fee2852672f846d91a2da14da7783a (patch) | |
| tree | a6ef16b7263252ae1b8069295ea9cbbae0d9467d /lib/Target/CellSPU/SPUHazardRecognizers.cpp | |
| parent | cbefa15de4821975bb99fc6d74b3bdb42b2df45c (diff) | |
| parent | b6714227eda5d499f7667fc865f931126a8dc488 (diff) | |
| download | external_llvm-059800f9e3fee2852672f846d91a2da14da7783a.zip external_llvm-059800f9e3fee2852672f846d91a2da14da7783a.tar.gz external_llvm-059800f9e3fee2852672f846d91a2da14da7783a.tar.bz2 | |
Merge remote-tracking branch 'upstream/master' into merge-llvm
Conflicts:
lib/CodeGen/AsmPrinter/AsmPrinter.cpp
lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
lib/MC/MCAssembler.cpp
lib/Support/Atomic.cpp
lib/Support/Memory.cpp
lib/Target/ARM/ARMJITInfo.cpp
Change-Id: Ib339baf88df5b04870c8df1bedcfe1f877ccab8d
Diffstat (limited to 'lib/Target/CellSPU/SPUHazardRecognizers.cpp')
| -rw-r--r-- | lib/Target/CellSPU/SPUHazardRecognizers.cpp | 135 |
1 files changed, 0 insertions, 135 deletions
diff --git a/lib/Target/CellSPU/SPUHazardRecognizers.cpp b/lib/Target/CellSPU/SPUHazardRecognizers.cpp deleted file mode 100644 index 67a83f1..0000000 --- a/lib/Target/CellSPU/SPUHazardRecognizers.cpp +++ /dev/null @@ -1,135 +0,0 @@ -//===-- SPUHazardRecognizers.cpp - Cell Hazard Recognizer Impls -----------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file implements hazard recognizers for scheduling on Cell SPU -// processors. -// -//===----------------------------------------------------------------------===// - -#define DEBUG_TYPE "sched" - -#include "SPUHazardRecognizers.h" -#include "SPU.h" -#include "SPUInstrInfo.h" -#include "llvm/CodeGen/ScheduleDAG.h" -#include "llvm/CodeGen/SelectionDAGNodes.h" -#include "llvm/Support/Debug.h" -#include "llvm/Support/raw_ostream.h" -using namespace llvm; - -//===----------------------------------------------------------------------===// -// Cell SPU hazard recognizer -// -// This is the pipeline hazard recognizer for the Cell SPU processor. It does -// very little right now. -//===----------------------------------------------------------------------===// - -/// Return the pipeline hazard type encountered or generated by this -/// instruction. Currently returns NoHazard. -/// -/// \return NoHazard -ScheduleHazardRecognizer::HazardType -SPUHazardRecognizer::getHazardType(SUnit *SU, int Stalls) -{ - // Initial thoughts on how to do this, but this code cannot work unless the - // function's prolog and epilog code are also being scheduled so that we can - // accurately determine which pipeline is being scheduled. -#if 0 - assert(Stalls == 0 && "SPU hazards don't yet support scoreboard lookahead"); - - const SDNode *Node = SU->getNode()->getFlaggedMachineNode(); - ScheduleHazardRecognizer::HazardType retval = NoHazard; - bool mustBeOdd = false; - - switch (Node->getOpcode()) { - case SPU::LQDv16i8: - case SPU::LQDv8i16: - case SPU::LQDv4i32: - case SPU::LQDv4f32: - case SPU::LQDv2f64: - case SPU::LQDr128: - case SPU::LQDr64: - case SPU::LQDr32: - case SPU::LQDr16: - case SPU::LQAv16i8: - case SPU::LQAv8i16: - case SPU::LQAv4i32: - case SPU::LQAv4f32: - case SPU::LQAv2f64: - case SPU::LQAr128: - case SPU::LQAr64: - case SPU::LQAr32: - case SPU::LQXv4i32: - case SPU::LQXr128: - case SPU::LQXr64: - case SPU::LQXr32: - case SPU::LQXr16: - case SPU::STQDv16i8: - case SPU::STQDv8i16: - case SPU::STQDv4i32: - case SPU::STQDv4f32: - case SPU::STQDv2f64: - case SPU::STQDr128: - case SPU::STQDr64: - case SPU::STQDr32: - case SPU::STQDr16: - case SPU::STQDr8: - case SPU::STQAv16i8: - case SPU::STQAv8i16: - case SPU::STQAv4i32: - case SPU::STQAv4f32: - case SPU::STQAv2f64: - case SPU::STQAr128: - case SPU::STQAr64: - case SPU::STQAr32: - case SPU::STQAr16: - case SPU::STQAr8: - case SPU::STQXv16i8: - case SPU::STQXv8i16: - case SPU::STQXv4i32: - case SPU::STQXv4f32: - case SPU::STQXv2f64: - case SPU::STQXr128: - case SPU::STQXr64: - case SPU::STQXr32: - case SPU::STQXr16: - case SPU::STQXr8: - case SPU::RET: - mustBeOdd = true; - break; - default: - // Assume that this instruction can be on the even pipe - break; - } - - if (mustBeOdd && !EvenOdd) - retval = Hazard; - - DEBUG(errs() << "SPUHazardRecognizer EvenOdd " << EvenOdd << " Hazard " - << retval << "\n"); - EvenOdd ^= 1; - return retval; -#else - return NoHazard; -#endif -} - -void SPUHazardRecognizer::EmitInstruction(SUnit *SU) -{ -} - -void SPUHazardRecognizer::AdvanceCycle() -{ - DEBUG(errs() << "SPUHazardRecognizer::AdvanceCycle\n"); -} - -void SPUHazardRecognizer::EmitNoop() -{ - AdvanceCycle(); -} |
