CellSPU:

- Fix v2[if]64 vector insertion code before IBM files a bug report.
- Ensure that zero (0) offsets relative to $sp don't trip an assert
  (add $sp, 0 gets legalized to $sp alone, tripping an assert)
- Shuffle masks passed to SPUISD::SHUFB are now v16i8 or v4i32


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60358 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 2 insertions, 2 deletions

diff --git a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
index a2144d3..8d65cf9 100644
--- a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
+++ b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
@@ -593,8 +593,8 @@ SPUDAGToDAGISel::SelectXFormAddr(SDValue Op, SDValue N, SDValue &Base,
       && !SelectDFormAddr(Op, N, Base, Index)) {
     // If the address is neither A-form or D-form, punt and use an X-form
     // address:
-    Base = N.getOperand(0);
-    Index = N.getOperand(1);
+    Base = N.getOperand(1);
+    Index = N.getOperand(0);
     return true;
   }