diff options
author | Scott Michel <scottm@aero.org> | 2009-01-03 00:27:53 +0000 |
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committer | Scott Michel <scottm@aero.org> | 2009-01-03 00:27:53 +0000 |
commit | 52d0001cfc7cc83c69f20430cf9039a798adc10b (patch) | |
tree | 40041a487d3d6e21622e5c283471626b6c2a21d2 /lib/Target/CellSPU/SPUInstrInfo.h | |
parent | 3d45f53b7a2cbc336e4980ccb3a41ba2c3874ff4 (diff) | |
download | external_llvm-52d0001cfc7cc83c69f20430cf9039a798adc10b.zip external_llvm-52d0001cfc7cc83c69f20430cf9039a798adc10b.tar.gz external_llvm-52d0001cfc7cc83c69f20430cf9039a798adc10b.tar.bz2 |
CellSPU:
- Remove custom lowering for BRCOND
- Add remaining functionality for branches in SPUInstrInfo, such as branch
condition reversal and load/store folding. Updated BrCond test to reflect
branch reversal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61597 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/CellSPU/SPUInstrInfo.h')
-rw-r--r-- | lib/Target/CellSPU/SPUInstrInfo.h | 47 |
1 files changed, 29 insertions, 18 deletions
diff --git a/lib/Target/CellSPU/SPUInstrInfo.h b/lib/Target/CellSPU/SPUInstrInfo.h index 27766ba..bc57e15 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.h +++ b/lib/Target/CellSPU/SPUInstrInfo.h @@ -23,6 +23,19 @@ namespace llvm { class SPUInstrInfo : public TargetInstrInfoImpl { SPUTargetMachine &TM; const SPURegisterInfo RI; + protected: + virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, + MachineInstr* MI, + const SmallVectorImpl<unsigned> &Ops, + int FrameIndex) const; + + virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, + MachineInstr* MI, + const SmallVectorImpl<unsigned> &Ops, + MachineInstr* LoadMI) const { + return 0; + } + public: explicit SPUInstrInfo(SPUTargetMachine &tm); @@ -34,7 +47,7 @@ namespace llvm { /// getPointerRegClass - Return the register class to use to hold pointers. /// This is used for addressing modes. - virtual const TargetRegisterClass *getPointerRegClass() const; + virtual const TargetRegisterClass *getPointerRegClass() const; // Return true if the instruction is a register to register move and // leave the source and dest operands in the passed parameters. @@ -47,13 +60,13 @@ namespace llvm { int &FrameIndex) const; unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const; - + virtual bool copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC) const; - + //! Store a register to a stack slot, based on its register class. virtual void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, @@ -77,27 +90,25 @@ namespace llvm { SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const; - - //! Fold spills into load/store instructions - virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, - MachineInstr* MI, - const SmallVectorImpl<unsigned> &Ops, - int FrameIndex) const; - //! Fold any load/store to an operand - virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, - MachineInstr* MI, - const SmallVectorImpl<unsigned> &Ops, - MachineInstr* LoadMI) const { - return 0; - } + //! Return true if the specified load or store can be folded + virtual + bool canFoldMemoryOperand(const MachineInstr *MI, + const SmallVectorImpl<unsigned> &Ops) const; + + //! Return true if the specified block does not fall through + virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const; + + //! Reverses a branch's condition, returning false on success. + virtual + bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond) const; - + virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; - + virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond) const; |