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author | Scott Michel <scottm@aero.org> | 2008-12-30 23:28:25 +0000 |
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committer | Scott Michel <scottm@aero.org> | 2008-12-30 23:28:25 +0000 |
commit | 02d711b93e3e0d2f0dae278360abe35305913e23 (patch) | |
tree | 8e85a3e48020ea52de566e67942de5b319c180fd /lib/Target/CellSPU/SPUNodes.td | |
parent | 998dee96d3ca506cf73a617c0b7fc7f0e467a127 (diff) | |
download | external_llvm-02d711b93e3e0d2f0dae278360abe35305913e23.zip external_llvm-02d711b93e3e0d2f0dae278360abe35305913e23.tar.gz external_llvm-02d711b93e3e0d2f0dae278360abe35305913e23.tar.bz2 |
- Start moving target-dependent nodes that could be represented by an
instruction sequence and cannot ordinarily be simplified by DAGcombine
into the various target description files or SPUDAGToDAGISel.cpp.
This makes some 64-bit operations legal.
- Eliminate target-dependent ISD enums.
- Update tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61508 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/CellSPU/SPUNodes.td')
-rw-r--r-- | lib/Target/CellSPU/SPUNodes.td | 29 |
1 files changed, 0 insertions, 29 deletions
diff --git a/lib/Target/CellSPU/SPUNodes.td b/lib/Target/CellSPU/SPUNodes.td index 5cf229e..89a52ee 100644 --- a/lib/Target/CellSPU/SPUNodes.td +++ b/lib/Target/CellSPU/SPUNodes.td @@ -87,24 +87,6 @@ def SPUcntb : SDNode<"SPUISD::CNTB", SDTIntUnaryOp>; // SPUISelLowering.h): def SPUshuffle: SDNode<"SPUISD::SHUFB", SDT_SPUshuffle, []>; -// SPU 16-bit multiply -def SPUmpy_vec: SDNode<"SPUISD::MPY", SPUVecBinop, []>; - -// SPU multiply unsigned, used in instruction lowering for v4i32 -// multiplies: -def SPUmpyu_vec: SDNode<"SPUISD::MPYU", SPUVecBinop, []>; -def SPUmpyu_int: SDNode<"SPUISD::MPYU", SDTIntBinOp, []>; - -// SPU 16-bit multiply high x low, shift result 16-bits -// Used to compute intermediate products for 32-bit multiplies -def SPUmpyh_vec: SDNode<"SPUISD::MPYH", SPUVecBinop, []>; -def SPUmpyh_int: SDNode<"SPUISD::MPYH", SDTIntBinOp, []>; - -// SPU 16-bit multiply high x high, 32-bit product -// Used to compute intermediate products for 16-bit multiplies -def SPUmpyhh_vec: SDNode<"SPUISD::MPYHH", SPUVecBinop, []>; -def SPUmpyhh_int: SDNode<"SPUISD::MPYHH", SDTIntBinOp, []>; - // Shift left quadword by bits and bytes def SPUshlquad_l_bits: SDNode<"SPUISD::SHLQUAD_L_BITS", SPUvecshift_type, []>; def SPUshlquad_l_bytes: SDNode<"SPUISD::SHLQUAD_L_BYTES", SPUvecshift_type, []>; @@ -117,11 +99,6 @@ def SPUvec_sra: SDNode<"SPUISD::VEC_SRA", SPUvecshift_type, []>; def SPUvec_rotl: SDNode<"SPUISD::VEC_ROTL", SPUvecshift_type, []>; def SPUvec_rotr: SDNode<"SPUISD::VEC_ROTR", SPUvecshift_type, []>; -def SPUrotquad_rz_bytes: SDNode<"SPUISD::ROTQUAD_RZ_BYTES", - SPUvecshift_type, []>; -def SPUrotquad_rz_bits: SDNode<"SPUISD::ROTQUAD_RZ_BITS", - SPUvecshift_type, []>; - // Vector rotate left, bits shifted out of the left are rotated in on the right def SPUrotbytes_left: SDNode<"SPUISD::ROTBYTES_LEFT", SPUvecshift_type, []>; @@ -141,12 +118,6 @@ def SPUselb: SDNode<"SPUISD::SELB", SPUselb_type, []>; // SPU gather bits instruction: def SPUgatherbits: SDNode<"SPUISD::GATHER_BITS", SPUgatherbits_type, []>; -// SPU floating point interpolate -def SPUinterpolate : SDNode<"SPUISD::FPInterp", SDTFPBinOp, []>; - -// SPU floating point reciprocal estimate (used for fdiv) -def SPUreciprocalEst: SDNode<"SPUISD::FPRecipEst", SDTFPUnaryOp, []>; - def SDTprefslot2vec: SDTypeProfile<1, 1, []>; def SPUprefslot2vec: SDNode<"SPUISD::PREFSLOT2VEC", SDTprefslot2vec, []>; |