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author | Scott Michel <scottm@aero.org> | 2008-12-29 03:23:36 +0000 |
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committer | Scott Michel <scottm@aero.org> | 2008-12-29 03:23:36 +0000 |
commit | 1df30c4061a6b6faaf9641f72b1741a0af4aa532 (patch) | |
tree | c353db2898593ed4ca285f29743234130626daae /lib/Target/CellSPU/SPUNodes.td | |
parent | 845145f8b5f7feb8617bcfcfd3803ef80b17765d (diff) | |
download | external_llvm-1df30c4061a6b6faaf9641f72b1741a0af4aa532.zip external_llvm-1df30c4061a6b6faaf9641f72b1741a0af4aa532.tar.gz external_llvm-1df30c4061a6b6faaf9641f72b1741a0af4aa532.tar.bz2 |
- Various '#if 0' cleanups.
- Move v4i32, i32 mul into SPUInstrInfo.td, with a few more instruction
cleanups there as well.
- Make SMUL_LOHI, UMUL_LOHI competely illegal for Cell SPU, to better
assist Chris to see the problem in bug 3101.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61464 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/CellSPU/SPUNodes.td')
-rw-r--r-- | lib/Target/CellSPU/SPUNodes.td | 30 |
1 files changed, 12 insertions, 18 deletions
diff --git a/lib/Target/CellSPU/SPUNodes.td b/lib/Target/CellSPU/SPUNodes.td index b22c6b5..5cf229e 100644 --- a/lib/Target/CellSPU/SPUNodes.td +++ b/lib/Target/CellSPU/SPUNodes.td @@ -35,17 +35,12 @@ def SDT_SPUshuffle : SDTypeProfile<1, 3, [ SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2> ]>; -// Unary, binary v16i8 operator type constraints: -def SPUv16i8_binop: SDTypeProfile<1, 2, [ - SDTCisVT<0, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>; +// Vector binary operator type constraints (needs a further constraint to +// ensure that operand 0 is a vector...): -// Binary v8i16 operator type constraints: -def SPUv8i16_binop: SDTypeProfile<1, 2, [ - SDTCisVT<0, v8i16>, SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>; - -// Binary v4i32 operator type constraints: -def SPUv4i32_binop: SDTypeProfile<1, 2, [ - SDTCisVT<0, v4i32>, SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>; +def SPUVecBinop: SDTypeProfile<1, 2, [ + SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2> +]>; // Trinary operators, e.g., addx, carry generate def SPUIntTrinaryOp : SDTypeProfile<1, 3, [ @@ -93,23 +88,22 @@ def SPUcntb : SDNode<"SPUISD::CNTB", SDTIntUnaryOp>; def SPUshuffle: SDNode<"SPUISD::SHUFB", SDT_SPUshuffle, []>; // SPU 16-bit multiply -def SPUmpy_v16i8: SDNode<"SPUISD::MPY", SPUv16i8_binop, []>; -def SPUmpy_v8i16: SDNode<"SPUISD::MPY", SPUv8i16_binop, []>; -def SPUmpy_v4i32: SDNode<"SPUISD::MPY", SPUv4i32_binop, []>; +def SPUmpy_vec: SDNode<"SPUISD::MPY", SPUVecBinop, []>; // SPU multiply unsigned, used in instruction lowering for v4i32 // multiplies: -def SPUmpyu_v4i32: SDNode<"SPUISD::MPYU", SPUv4i32_binop, []>; -def SPUmpyu_i32: SDNode<"SPUISD::MPYU", SDTIntBinOp, []>; +def SPUmpyu_vec: SDNode<"SPUISD::MPYU", SPUVecBinop, []>; +def SPUmpyu_int: SDNode<"SPUISD::MPYU", SDTIntBinOp, []>; // SPU 16-bit multiply high x low, shift result 16-bits // Used to compute intermediate products for 32-bit multiplies -def SPUmpyh_v4i32: SDNode<"SPUISD::MPYH", SPUv4i32_binop, []>; -def SPUmpyh_i32: SDNode<"SPUISD::MPYH", SDTIntBinOp, []>; +def SPUmpyh_vec: SDNode<"SPUISD::MPYH", SPUVecBinop, []>; +def SPUmpyh_int: SDNode<"SPUISD::MPYH", SDTIntBinOp, []>; // SPU 16-bit multiply high x high, 32-bit product // Used to compute intermediate products for 16-bit multiplies -def SPUmpyhh_v8i16: SDNode<"SPUISD::MPYHH", SPUv8i16_binop, []>; +def SPUmpyhh_vec: SDNode<"SPUISD::MPYHH", SPUVecBinop, []>; +def SPUmpyhh_int: SDNode<"SPUISD::MPYHH", SDTIntBinOp, []>; // Shift left quadword by bits and bytes def SPUshlquad_l_bits: SDNode<"SPUISD::SHLQUAD_L_BITS", SPUvecshift_type, []>; |