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author | Scott Michel <scottm@aero.org> | 2009-01-15 04:41:47 +0000 |
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committer | Scott Michel <scottm@aero.org> | 2009-01-15 04:41:47 +0000 |
commit | 94bd57e154088f2d45c465e73f896f64f6da4ade (patch) | |
tree | 54cfa11f05e8040e9d7d18949bbeb5d23ecfce5e /lib/Target/CellSPU/SPUNodes.td | |
parent | f9b1d79a549269f0630edd4893c654953ae07a6a (diff) | |
download | external_llvm-94bd57e154088f2d45c465e73f896f64f6da4ade.zip external_llvm-94bd57e154088f2d45c465e73f896f64f6da4ade.tar.gz external_llvm-94bd57e154088f2d45c465e73f896f64f6da4ade.tar.bz2 |
- Convert remaining i64 custom lowering into custom instruction emission
sequences in SPUDAGToDAGISel.cpp and SPU64InstrInfo.td, killing custom
DAG node types as needed.
- i64 mul is now a legal instruction, but emits an instruction sequence
that stretches tblgen and the imagination, as well as violating laws of
several small countries and most southern US states (just kidding, but
looking at a function with 80+ parameters is really weird and just plain
wrong.)
- Update tests as needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62254 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/CellSPU/SPUNodes.td')
-rw-r--r-- | lib/Target/CellSPU/SPUNodes.td | 24 |
1 files changed, 16 insertions, 8 deletions
diff --git a/lib/Target/CellSPU/SPUNodes.td b/lib/Target/CellSPU/SPUNodes.td index cae6023..87c4115 100644 --- a/lib/Target/CellSPU/SPUNodes.td +++ b/lib/Target/CellSPU/SPUNodes.td @@ -61,18 +61,20 @@ def SPUselb_type: SDTypeProfile<1, 3, [ def SPUvecshift_type: SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>, SDTCisInt<2>]>; +// "marker" type for i64 operators that need a shuffle mask +// (i.e., uses cg or bg or another instruction that needs to +// use shufb to get things in the right place.) +// Op0: The result +// Op1, 2: LHS, RHS +// Op3: Carry-generate shuffle mask + +def SPUmarker_type : SDTypeProfile<1, 3, [ + SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2> ]>; + //===----------------------------------------------------------------------===// // Synthetic/pseudo-instructions //===----------------------------------------------------------------------===// -/// Add extended, carry generate: -def SPUaddx : SDNode<"SPUISD::ADD_EXTENDED", SPUIntTrinaryOp, []>; -def SPUcarry_gen : SDNode<"SPUISD::CARRY_GENERATE", SDTIntBinOp, []>; - -// Subtract extended, borrow generate -def SPUsubx : SDNode<"SPUISD::SUB_EXTENDED", SPUIntTrinaryOp, []>; -def SPUborrow_gen : SDNode<"SPUISD::BORROW_GENERATE", SDTIntBinOp, []>; - // SPU CNTB: def SPUcntb : SDNode<"SPUISD::CNTB", SDTIntUnaryOp>; @@ -127,6 +129,12 @@ def SPUaform : SDNode<"SPUISD::AFormAddr", SDTIntBinOp, []>; // Indirect [D-Form "imm($reg)" and X-Form "$reg($reg)"] addresses def SPUindirect : SDNode<"SPUISD::IndirectAddr", SDTIntBinOp, []>; +// i64 markers: supplies extra operands used to generate the i64 operator +// instruction sequences +def SPUadd64 : SDNode<"SPUISD::ADD64_MARKER", SPUmarker_type, []>; +def SPUsub64 : SDNode<"SPUISD::SUB64_MARKER", SPUmarker_type, []>; +def SPUmul64 : SDNode<"SPUISD::MUL64_MARKER", SPUmarker_type, []>; + //===----------------------------------------------------------------------===// // Constraints: (taken from PPCInstrInfo.td) //===----------------------------------------------------------------------===// |