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author | Scott Michel <scottm@aero.org> | 2008-12-27 04:51:36 +0000 |
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committer | Scott Michel <scottm@aero.org> | 2008-12-27 04:51:36 +0000 |
commit | f0569be4a948c7ed816bfa2b8774a5a18458ee23 (patch) | |
tree | 541905fcbd5e64ef95599b1ca3c4182adc972688 /lib/Target/CellSPU/SPUNodes.td | |
parent | 1323e8bf6a7bec163c5d43006f5b3b78042cef61 (diff) | |
download | external_llvm-f0569be4a948c7ed816bfa2b8774a5a18458ee23.zip external_llvm-f0569be4a948c7ed816bfa2b8774a5a18458ee23.tar.gz external_llvm-f0569be4a948c7ed816bfa2b8774a5a18458ee23.tar.bz2 |
- Remove Tilmann's custom truncate lowering: it completely hosed over
DAGcombine's ability to find reasons to remove truncates when they were not
needed. Consequently, the CellSPU backend would produce correct, but _really
slow and horrible_, code.
Replaced with instruction sequences that do the equivalent truncation in
SPUInstrInfo.td.
- Re-examine how unaligned loads and stores work. Generated unaligned
load code has been tested on the CellSPU hardware; see the i32operations.c
and i64operations.c in CodeGen/CellSPU/useful-harnesses. (While they may be
toy test code, it does prove that some real world code does compile
correctly.)
- Fix truncating stores in bug 3193 (note: unpack_df.ll will still make llc
fault because i64 ult is not yet implemented.)
- Added i64 eq and neq for setcc and select/setcc; started new instruction
information file for them in SPU64InstrInfo.td. Additional i64 operations
should be added to this file and not to SPUInstrInfo.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61447 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/CellSPU/SPUNodes.td')
-rw-r--r-- | lib/Target/CellSPU/SPUNodes.td | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/lib/Target/CellSPU/SPUNodes.td b/lib/Target/CellSPU/SPUNodes.td index 1ed1e3b..b22c6b5 100644 --- a/lib/Target/CellSPU/SPUNodes.td +++ b/lib/Target/CellSPU/SPUNodes.td @@ -66,6 +66,13 @@ def SPUselb_type: SDTypeProfile<1, 3, [ def SPUvecshift_type: SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>, SDTCisInt<2>]>; +// SPU gather bits: +// This instruction looks at each vector (word|halfword|byte) slot's low bit +// and forms a mask in the low order bits of the first word's preferred slot. +def SPUgatherbits_type: SDTypeProfile<1, 1, [ + /* no type constraints defined */ +]>; + //===----------------------------------------------------------------------===// // Synthetic/pseudo-instructions //===----------------------------------------------------------------------===// @@ -137,14 +144,17 @@ def SPUselmask: SDNode<"SPUISD::SELECT_MASK", SPUselmask_type, []>; // SPU select bits instruction def SPUselb: SDNode<"SPUISD::SELB", SPUselb_type, []>; +// SPU gather bits instruction: +def SPUgatherbits: SDNode<"SPUISD::GATHER_BITS", SPUgatherbits_type, []>; + // SPU floating point interpolate def SPUinterpolate : SDNode<"SPUISD::FPInterp", SDTFPBinOp, []>; // SPU floating point reciprocal estimate (used for fdiv) def SPUreciprocalEst: SDNode<"SPUISD::FPRecipEst", SDTFPUnaryOp, []>; -def SDTpromote_scalar: SDTypeProfile<1, 1, []>; -def SPUpromote_scalar: SDNode<"SPUISD::PROMOTE_SCALAR", SDTpromote_scalar, []>; +def SDTprefslot2vec: SDTypeProfile<1, 1, []>; +def SPUprefslot2vec: SDNode<"SPUISD::PREFSLOT2VEC", SDTprefslot2vec, []>; def SPU_vec_demote : SDTypeProfile<1, 1, []>; def SPUvec2prefslot: SDNode<"SPUISD::VEC2PREFSLOT", SPU_vec_demote, []>; |