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authorEli Friedman <eli.friedman@gmail.com>2011-07-27 22:21:52 +0000
committerEli Friedman <eli.friedman@gmail.com>2011-07-27 22:21:52 +0000
commit14648468011c92a4210f8118721d58c25043daf8 (patch)
tree287882ae779b0bd87f8e9a7996fae00d99785a59 /lib/Target/CellSPU
parent144da2c8f03834e76ddb617498be7ed864a5c192 (diff)
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Code generation for 'fence' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136283 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/CellSPU')
-rw-r--r--lib/Target/CellSPU/SPUISelLowering.cpp1
1 files changed, 1 insertions, 0 deletions
diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp
index 1c533a9..59337bc 100644
--- a/lib/Target/CellSPU/SPUISelLowering.cpp
+++ b/lib/Target/CellSPU/SPUISelLowering.cpp
@@ -174,6 +174,7 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
// SPU has no intrinsics for these particular operations:
setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
+ setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
// SPU has no division/remainder instructions
setOperationAction(ISD::SREM, MVT::i8, Expand);