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| author | Duncan Sands <baldrick@free.fr> | 2011-09-06 19:07:46 +0000 |
|---|---|---|
| committer | Duncan Sands <baldrick@free.fr> | 2011-09-06 19:07:46 +0000 |
| commit | 28b77e968d2b01fc9da724762bd8ddcd80650e32 (patch) | |
| tree | 711ee16dd99789ee82f4891e436cdd38535667da /lib/Target/CellSPU | |
| parent | 4a51708448e8958d8d1a375c055f1b98c8e20926 (diff) | |
| download | external_llvm-28b77e968d2b01fc9da724762bd8ddcd80650e32.zip external_llvm-28b77e968d2b01fc9da724762bd8ddcd80650e32.tar.gz external_llvm-28b77e968d2b01fc9da724762bd8ddcd80650e32.tar.bz2 | |
Add codegen support for vector select (in the IR this means a select
with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons. Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all"). Patch mostly by
Nadav Rotem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139159 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/CellSPU')
| -rw-r--r-- | lib/Target/CellSPU/SPUISelLowering.cpp | 3 | ||||
| -rw-r--r-- | lib/Target/CellSPU/SPUISelLowering.h | 2 |
2 files changed, 3 insertions, 2 deletions
diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp index 1a081e9..cfd29cf 100644 --- a/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/lib/Target/CellSPU/SPUISelLowering.cpp @@ -439,6 +439,7 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM) setOperationAction(ISD::FDIV, MVT::v4f32, Legal); setBooleanContents(ZeroOrNegativeOneBooleanContent); + setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); // FIXME: Is this correct? setStackPointerRegisterToSaveRestore(SPU::R1); @@ -498,7 +499,7 @@ SPUTargetLowering::getTargetNodeName(unsigned Opcode) const // Return the Cell SPU's SETCC result type //===----------------------------------------------------------------------===// -MVT::SimpleValueType SPUTargetLowering::getSetCCResultType(EVT VT) const { +EVT SPUTargetLowering::getSetCCResultType(EVT VT) const { // i8, i16 and i32 are valid SETCC result types MVT::SimpleValueType retval; diff --git a/lib/Target/CellSPU/SPUISelLowering.h b/lib/Target/CellSPU/SPUISelLowering.h index 91bbdf2..aa4a168 100644 --- a/lib/Target/CellSPU/SPUISelLowering.h +++ b/lib/Target/CellSPU/SPUISelLowering.h @@ -107,7 +107,7 @@ namespace llvm { virtual const char *getTargetNodeName(unsigned Opcode) const; /// getSetCCResultType - Return the ValueType for ISD::SETCC - virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const; + virtual EVT getSetCCResultType(EVT VT) const; virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; } |