Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155188 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 35 insertions, 35 deletions

diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp
index 0623741..da6ed94 100644
--- a/lib/Target/CellSPU/SPUISelLowering.cpp
+++ b/lib/Target/CellSPU/SPUISelLowering.cpp
@@ -100,13 +100,13 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
   setLibcallName(RTLIB::DIV_F64, "__fast_divdf3");
 
   // Set up the SPU's register classes:
-  addRegisterClass(MVT::i8,   SPU::R8CRegisterClass);
-  addRegisterClass(MVT::i16,  SPU::R16CRegisterClass);
-  addRegisterClass(MVT::i32,  SPU::R32CRegisterClass);
-  addRegisterClass(MVT::i64,  SPU::R64CRegisterClass);
-  addRegisterClass(MVT::f32,  SPU::R32FPRegisterClass);
-  addRegisterClass(MVT::f64,  SPU::R64FPRegisterClass);
-  addRegisterClass(MVT::i128, SPU::GPRCRegisterClass);
+  addRegisterClass(MVT::i8,   &SPU::R8CRegClass);
+  addRegisterClass(MVT::i16,  &SPU::R16CRegClass);
+  addRegisterClass(MVT::i32,  &SPU::R32CRegClass);
+  addRegisterClass(MVT::i64,  &SPU::R64CRegClass);
+  addRegisterClass(MVT::f32,  &SPU::R32FPRegClass);
+  addRegisterClass(MVT::f64,  &SPU::R64FPRegClass);
+  addRegisterClass(MVT::i128, &SPU::GPRCRegClass);
 
   // SPU has no sign or zero extended loads for i1, i8, i16:
   setLoadExtAction(ISD::EXTLOAD,  MVT::i1, Promote);
@@ -397,12 +397,12 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
 
   // First set operation action for all vector types to expand. Then we
   // will selectively turn on ones that can be effectively codegen'd.
-  addRegisterClass(MVT::v16i8, SPU::VECREGRegisterClass);
-  addRegisterClass(MVT::v8i16, SPU::VECREGRegisterClass);
-  addRegisterClass(MVT::v4i32, SPU::VECREGRegisterClass);
-  addRegisterClass(MVT::v2i64, SPU::VECREGRegisterClass);
-  addRegisterClass(MVT::v4f32, SPU::VECREGRegisterClass);
-  addRegisterClass(MVT::v2f64, SPU::VECREGRegisterClass);
+  addRegisterClass(MVT::v16i8, &SPU::VECREGRegClass);
+  addRegisterClass(MVT::v8i16, &SPU::VECREGRegClass);
+  addRegisterClass(MVT::v4i32, &SPU::VECREGRegClass);
+  addRegisterClass(MVT::v2i64, &SPU::VECREGRegClass);
+  addRegisterClass(MVT::v4f32, &SPU::VECREGRegClass);
+  addRegisterClass(MVT::v2f64, &SPU::VECREGRegClass);
 
   for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
        i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
@@ -3139,16 +3139,16 @@ SPUTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
     case 'b':   // R1-R31
     case 'r':   // R0-R31
       if (VT == MVT::i64)
-        return std::make_pair(0U, SPU::R64CRegisterClass);
-      return std::make_pair(0U, SPU::R32CRegisterClass);
+        return std::make_pair(0U, &SPU::R64CRegClass);
+      return std::make_pair(0U, &SPU::R32CRegClass);
     case 'f':
       if (VT == MVT::f32)
-        return std::make_pair(0U, SPU::R32FPRegisterClass);
-      else if (VT == MVT::f64)
-        return std::make_pair(0U, SPU::R64FPRegisterClass);
+        return std::make_pair(0U, &SPU::R32FPRegClass);
+      if (VT == MVT::f64)
+        return std::make_pair(0U, &SPU::R64FPRegClass);
       break;
     case 'v':
-      return std::make_pair(0U, SPU::GPRCRegisterClass);
+      return std::make_pair(0U, &SPU::GPRCRegClass);
     }
   }
 
diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp
index a30de46..b599d7b 100644
--- a/lib/Target/CellSPU/SPUInstrInfo.cpp
+++ b/lib/Target/CellSPU/SPUInstrInfo.cpp
@@ -143,21 +143,21 @@ SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
                                   const TargetRegisterInfo *TRI) const {
   unsigned opc;
   bool isValidFrameIdx = (FrameIdx < SPUFrameLowering::maxFrameOffset());
-  if (RC == SPU::GPRCRegisterClass)
+  if (RC == &SPU::GPRCRegClass)
     opc = isValidFrameIdx ? SPU::STQDr128 : SPU::STQXr128;
-  else if (RC == SPU::R64CRegisterClass)
+  else if (RC == &SPU::R64CRegClass)
     opc = isValidFrameIdx ? SPU::STQDr64 : SPU::STQXr64;
-  else if (RC == SPU::R64FPRegisterClass)
+  else if (RC == &SPU::R64FPRegClass)
     opc = isValidFrameIdx ? SPU::STQDr64 : SPU::STQXr64;
-  else if (RC == SPU::R32CRegisterClass)
+  else if (RC == &SPU::R32CRegClass)
     opc = isValidFrameIdx ? SPU::STQDr32 : SPU::STQXr32;
-  else if (RC == SPU::R32FPRegisterClass)
+  else if (RC == &SPU::R32FPRegClass)
     opc = isValidFrameIdx ? SPU::STQDr32 : SPU::STQXr32;
-  else if (RC == SPU::R16CRegisterClass)
+  else if (RC == &SPU::R16CRegClass)
     opc = isValidFrameIdx ? SPU::STQDr16 : SPU::STQXr16;
-  else if (RC == SPU::R8CRegisterClass)
+  else if (RC == &SPU::R8CRegClass)
     opc = isValidFrameIdx ? SPU::STQDr8 : SPU::STQXr8;
-  else if (RC == SPU::VECREGRegisterClass)
+  else if (RC == &SPU::VECREGRegClass)
     opc = isValidFrameIdx ? SPU::STQDv16i8 : SPU::STQXv16i8;
   else
     llvm_unreachable("Unknown regclass!");
@@ -176,21 +176,21 @@ SPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
                                    const TargetRegisterInfo *TRI) const {
   unsigned opc;
   bool isValidFrameIdx = (FrameIdx < SPUFrameLowering::maxFrameOffset());
-  if (RC == SPU::GPRCRegisterClass)
+  if (RC == &SPU::GPRCRegClass)
     opc = isValidFrameIdx ? SPU::LQDr128 : SPU::LQXr128;
-  else if (RC == SPU::R64CRegisterClass)
+  else if (RC == &SPU::R64CRegClass)
     opc = isValidFrameIdx ? SPU::LQDr64 : SPU::LQXr64;
-  else if (RC == SPU::R64FPRegisterClass)
+  else if (RC == &SPU::R64FPRegClass)
     opc = isValidFrameIdx ? SPU::LQDr64 : SPU::LQXr64;
-  else if (RC == SPU::R32CRegisterClass)
+  else if (RC == &SPU::R32CRegClass)
     opc = isValidFrameIdx ? SPU::LQDr32 : SPU::LQXr32;
-  else if (RC == SPU::R32FPRegisterClass)
+  else if (RC == &SPU::R32FPRegClass)
     opc = isValidFrameIdx ? SPU::LQDr32 : SPU::LQXr32;
-  else if (RC == SPU::R16CRegisterClass)
+  else if (RC == &SPU::R16CRegClass)
     opc = isValidFrameIdx ? SPU::LQDr16 : SPU::LQXr16;
-  else if (RC == SPU::R8CRegisterClass)
+  else if (RC == &SPU::R8CRegClass)
     opc = isValidFrameIdx ? SPU::LQDr8 : SPU::LQXr8;
-  else if (RC == SPU::VECREGRegisterClass)
+  else if (RC == &SPU::VECREGRegClass)
     opc = isValidFrameIdx ? SPU::LQDv16i8 : SPU::LQXv16i8;
   else
     llvm_unreachable("Unknown regclass in loadRegFromStackSlot!");