diff options
| author | Kalle Raiskila <kalle.raiskila@nokia.com> | 2010-06-21 15:08:16 +0000 |
|---|---|---|
| committer | Kalle Raiskila <kalle.raiskila@nokia.com> | 2010-06-21 15:08:16 +0000 |
| commit | 951b229ccf95b187fb09734f6c37473d25c2c2b6 (patch) | |
| tree | 50b1208b860f6b7cf008253ae97ea47b26849773 /lib/Target/CellSPU | |
| parent | 91fdee125cc95c322064a6f1ad8fba169f7ecebe (diff) | |
| download | external_llvm-951b229ccf95b187fb09734f6c37473d25c2c2b6.zip external_llvm-951b229ccf95b187fb09734f6c37473d25c2c2b6.tar.gz external_llvm-951b229ccf95b187fb09734f6c37473d25c2c2b6.tar.bz2 | |
Mark the SPU 'lr' instruction to never have side effects.
This allows the fast regiser allocator to remove redundant
register moves.
Update a set of tests that depend on the register allocator
to be linear scan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106420 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/CellSPU')
| -rw-r--r-- | lib/Target/CellSPU/SPUInstrInfo.cpp | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp index 877d1c5..9dfe014 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.cpp +++ b/lib/Target/CellSPU/SPUInstrInfo.cpp @@ -164,11 +164,9 @@ SPUInstrInfo::isMoveInstr(const MachineInstr& MI, MI.getOperand(0).isReg() && MI.getOperand(1).isReg() && "invalid SPU OR<type>_<vec> or LR instruction!"); - if (MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) { sourceReg = MI.getOperand(1).getReg(); destReg = MI.getOperand(0).getReg(); return true; - } break; } case SPU::ORv16i8: |