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authorKalle Raiskila <kalle.raiskila@nokia.com>2010-08-04 13:59:48 +0000
committerKalle Raiskila <kalle.raiskila@nokia.com>2010-08-04 13:59:48 +0000
commitbc2697cca0fc58434b6177923d46612267781825 (patch)
treea264ef32142aae00f766fd37db278b4a7533598b /lib/Target/CellSPU
parentc575283675f7bd9f7cc40f06024ba6251c2d55a8 (diff)
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Make SPU backend handle insertelement and
store for "half vectors" git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110198 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/CellSPU')
-rw-r--r--lib/Target/CellSPU/SPUISelDAGToDAG.cpp3
-rw-r--r--lib/Target/CellSPU/SPUISelLowering.cpp5
-rw-r--r--lib/Target/CellSPU/SPUInstrInfo.td6
3 files changed, 12 insertions, 2 deletions
diff --git a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
index 9b8c2dd..e42417c 100644
--- a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
+++ b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
@@ -607,7 +607,8 @@ SPUDAGToDAGISel::DFormAddressPredicate(SDNode *Op, SDValue N, SDValue &Base,
return true;
} else if (Opc == ISD::Register
||Opc == ISD::CopyFromReg
- ||Opc == ISD::UNDEF) {
+ ||Opc == ISD::UNDEF
+ ||Opc == ISD::Constant) {
unsigned OpOpc = Op->getOpcode();
if (OpOpc == ISD::STORE || OpOpc == ISD::LOAD) {
diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp
index 3a945ce..7a6bb0f 100644
--- a/lib/Target/CellSPU/SPUISelLowering.cpp
+++ b/lib/Target/CellSPU/SPUISelLowering.cpp
@@ -2102,7 +2102,10 @@ static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
SDValue Pointer = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT,
DAG.getRegister(SPU::R1, PtrVT),
DAG.getConstant(Idx, PtrVT));
- SDValue ShufMask = DAG.getNode(SPUISD::SHUFFLE_MASK, dl, VT, Pointer);
+ // widen the mask when dealing with half vectors
+ EVT maskVT = EVT::getVectorVT(*(DAG.getContext()), VT.getVectorElementType(),
+ 128/ VT.getVectorElementType().getSizeInBits());
+ SDValue ShufMask = DAG.getNode(SPUISD::SHUFFLE_MASK, dl, maskVT, Pointer);
SDValue result =
DAG.getNode(SPUISD::SHUFB, dl, VT,
diff --git a/lib/Target/CellSPU/SPUInstrInfo.td b/lib/Target/CellSPU/SPUInstrInfo.td
index 803ce56..f1d0886 100644
--- a/lib/Target/CellSPU/SPUInstrInfo.td
+++ b/lib/Target/CellSPU/SPUInstrInfo.td
@@ -63,6 +63,7 @@ let canFoldAsLoad = 1 in {
def v2f64: LoadDFormVec<v2f64>;
def v2i32: LoadDFormVec<v2i32>;
+ def v2f32: LoadDFormVec<v2f32>;
def r128: LoadDForm<GPRC>;
def r64: LoadDForm<R64C>;
@@ -97,6 +98,7 @@ let canFoldAsLoad = 1 in {
def v2f64: LoadAFormVec<v2f64>;
def v2i32: LoadAFormVec<v2i32>;
+ def v2f32: LoadAFormVec<v2f32>;
def r128: LoadAForm<GPRC>;
def r64: LoadAForm<R64C>;
@@ -131,6 +133,7 @@ let canFoldAsLoad = 1 in {
def v2f64: LoadXFormVec<v2f64>;
def v2i32: LoadXFormVec<v2i32>;
+ def v2f32: LoadXFormVec<v2f32>;
def r128: LoadXForm<GPRC>;
def r64: LoadXForm<R64C>;
@@ -181,6 +184,7 @@ multiclass StoreDForms
def v2f64: StoreDFormVec<v2f64>;
def v2i32: StoreDFormVec<v2i32>;
+ def v2f32: StoreDFormVec<v2f32>;
def r128: StoreDForm<GPRC>;
def r64: StoreDForm<R64C>;
@@ -213,6 +217,7 @@ multiclass StoreAForms
def v2f64: StoreAFormVec<v2f64>;
def v2i32: StoreAFormVec<v2i32>;
+ def v2f32: StoreAFormVec<v2f32>;
def r128: StoreAForm<GPRC>;
def r64: StoreAForm<R64C>;
@@ -247,6 +252,7 @@ multiclass StoreXForms
def v2f64: StoreXFormVec<v2f64>;
def v2i32: StoreXFormVec<v2i32>;
+ def v2f32: StoreXFormVec<v2f32>;
def r128: StoreXForm<GPRC>;
def r64: StoreXForm<R64C>;