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| author | Andrew Trick <atrick@apple.com> | 2012-02-01 22:13:57 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-02-01 22:13:57 +0000 |
| commit | ee498d3254b86bceb4f441741e9f442990647ce6 (patch) | |
| tree | f2319c428f9e572162a0ca172a573da5ea39bcdf /lib/Target/Hexagon/Makefile | |
| parent | f18a9a2314542ad3b7a601b86969073519e19b0d (diff) | |
| download | external_llvm-ee498d3254b86bceb4f441741e9f442990647ce6.zip external_llvm-ee498d3254b86bceb4f441741e9f442990647ce6.tar.gz external_llvm-ee498d3254b86bceb4f441741e9f442990647ce6.tar.bz2 | |
VLIW specific scheduler framework that utilizes deterministic finite automaton (DFA).
This new scheduler plugs into the existing selection DAG scheduling framework. It is a top-down critical path scheduler that tracks register pressure and uses a DFA for pipeline modeling.
Patch by Sergei Larin!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149547 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Hexagon/Makefile')
| -rw-r--r-- | lib/Target/Hexagon/Makefile | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/lib/Target/Hexagon/Makefile b/lib/Target/Hexagon/Makefile index c936e92..34bc68d 100644 --- a/lib/Target/Hexagon/Makefile +++ b/lib/Target/Hexagon/Makefile @@ -16,6 +16,7 @@ BUILT_SOURCES = HexagonGenRegisterInfo.inc \ HexagonGenAsmWriter.inc \ HexagonGenDAGISel.inc HexagonGenSubtargetInfo.inc \ HexagonGenCallingConv.inc \ + HexagonGenDFAPacketizer.inc \ HexagonAsmPrinter.cpp DIRS = TargetInfo MCTargetDesc |