aboutsummaryrefslogtreecommitdiffstats
path: root/lib/Target/Hexagon
diff options
context:
space:
mode:
authorBenjamin Kramer <benny.kra@googlemail.com>2011-12-27 11:41:05 +0000
committerBenjamin Kramer <benny.kra@googlemail.com>2011-12-27 11:41:05 +0000
commit27baab62e7d6267d9b18e4665c6bb1b75dae10d4 (patch)
tree8a21976c7f97f5c8fd7970be26c2052d7b339fe4 /lib/Target/Hexagon
parent3738ccd7eb99d75cbe31777a98675e5e5c23fee3 (diff)
downloadexternal_llvm-27baab62e7d6267d9b18e4665c6bb1b75dae10d4.zip
external_llvm-27baab62e7d6267d9b18e4665c6bb1b75dae10d4.tar.gz
external_llvm-27baab62e7d6267d9b18e4665c6bb1b75dae10d4.tar.bz2
Clean up some Release build warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147289 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Hexagon')
-rw-r--r--lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp5
-rw-r--r--lib/Target/Hexagon/HexagonInstrInfo.cpp13
-rw-r--r--lib/Target/Hexagon/HexagonRegisterInfo.cpp20
3 files changed, 14 insertions, 24 deletions
diff --git a/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp b/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp
index cb73ae0..965d482 100644
--- a/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp
+++ b/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp
@@ -70,7 +70,6 @@ char HexagonExpandPredSpillCode::ID = 0;
bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) {
const HexagonInstrInfo *TII = QTM.getInstrInfo();
- const HexagonRegisterInfo *RegInfo = QTM.getRegisterInfo();
// Loop over all of the basic blocks.
for (MachineFunction::iterator MBBb = Fn.begin(), MBBe = Fn.end();
@@ -84,7 +83,7 @@ bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) {
if (Opc == Hexagon::STriw_pred) {
// STriw_pred [R30], ofst, SrcReg;
unsigned FP = MI->getOperand(0).getReg();
- assert(FP == RegInfo->getFrameRegister() &&
+ assert(FP == QTM.getRegisterInfo()->getFrameRegister() &&
"Not a Frame Pointer, Nor a Spill Slot");
assert(MI->getOperand(1).isImm() && "Not an offset");
int Offset = MI->getOperand(1).getImm();
@@ -129,7 +128,7 @@ bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) {
assert(Hexagon::PredRegsRegClass.contains(DstReg) &&
"Not a predicate register");
unsigned FP = MI->getOperand(1).getReg();
- assert(FP == RegInfo->getFrameRegister() &&
+ assert(FP == QTM.getRegisterInfo()->getFrameRegister() &&
"Not a Frame Pointer, Nor a Spill Slot");
assert(MI->getOperand(2).isImm() && "Not an offset");
int Offset = MI->getOperand(2).getImm();
diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp
index 69a50d7..ae42da7 100644
--- a/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -461,7 +461,7 @@ unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
} else if (VT == MVT::i64) {
TRC = Hexagon::DoubleRegsRegisterClass;
} else {
- assert(0 && "Cannot handle this register class");
+ llvm_unreachable("Cannot handle this register class");
}
unsigned NewReg = RegInfo.createVirtualRegister(TRC);
@@ -553,10 +553,6 @@ bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
case Hexagon::JMPR:
return false;
- return true;
-
- default:
- return true;
}
return true;
@@ -793,9 +789,8 @@ getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
case Hexagon::DEALLOC_RET_V4:
return !invertPredicate ? Hexagon::DEALLOC_RET_cPt_V4 :
Hexagon::DEALLOC_RET_cNotPt_V4;
- default:
- assert(false && "Unexpected predicable instruction");
}
+ llvm_unreachable("Unexpected predicable instruction");
}
@@ -1243,8 +1238,8 @@ isValidOffset(const int Opcode, const int Offset) const {
return true;
}
- assert(0 && "No offset range is defined for this opcode. Please define it in \
- the above switch statement!");
+ llvm_unreachable("No offset range is defined for this opcode. "
+ "Please define it in the above switch statement!");
}
diff --git a/lib/Target/Hexagon/HexagonRegisterInfo.cpp b/lib/Target/Hexagon/HexagonRegisterInfo.cpp
index 521e0c1..256f8b4 100644
--- a/lib/Target/Hexagon/HexagonRegisterInfo.cpp
+++ b/lib/Target/Hexagon/HexagonRegisterInfo.cpp
@@ -58,18 +58,16 @@ const unsigned* HexagonRegisterInfo::getCalleeSavedRegs(const MachineFunction
};
switch(Subtarget.getHexagonArchVersion()) {
+ case HexagonSubtarget::V1:
+ break;
case HexagonSubtarget::V2:
return CalleeSavedRegsV2;
- break;
case HexagonSubtarget::V3:
case HexagonSubtarget::V4:
return CalleeSavedRegsV3;
- break;
- default:
- const char *ErrorString =
- "Callee saved registers requested for unknown archtecture version";
- llvm_unreachable(ErrorString);
}
+ llvm_unreachable("Callee saved registers requested for unknown architecture "
+ "version");
}
BitVector HexagonRegisterInfo::getReservedRegs(const MachineFunction &MF)
@@ -106,18 +104,16 @@ HexagonRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
};
switch(Subtarget.getHexagonArchVersion()) {
+ case HexagonSubtarget::V1:
+ break;
case HexagonSubtarget::V2:
return CalleeSavedRegClassesV2;
- break;
case HexagonSubtarget::V3:
case HexagonSubtarget::V4:
return CalleeSavedRegClassesV3;
- break;
- default:
- const char *ErrorString =
- "Callee saved register classes requested for unknown archtecture version";
- llvm_unreachable(ErrorString);
}
+ llvm_unreachable("Callee saved register classes requested for unknown "
+ "architecture version");
}
void HexagonRegisterInfo::