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| author | Andrew Trick <atrick@apple.com> | 2013-05-29 22:03:55 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2013-05-29 22:03:55 +0000 |
| commit | 6e0b2a0cb0d398f175a5294bf0ad5488c714e8c2 (patch) | |
| tree | 8ef279826ff76c91b57c9f7ebb0d7ad09e62b561 /lib/Target/Hexagon | |
| parent | 8df6f4bc8be1680e98b9ce7a7bb868b129c016ab (diff) | |
| download | external_llvm-6e0b2a0cb0d398f175a5294bf0ad5488c714e8c2.zip external_llvm-6e0b2a0cb0d398f175a5294bf0ad5488c714e8c2.tar.gz external_llvm-6e0b2a0cb0d398f175a5294bf0ad5488c714e8c2.tar.bz2 | |
Order CALLSEQ_START and CALLSEQ_END nodes.
Fixes PR16146: gdb.base__call-ar-st.exp fails after
pre-RA-sched=source fixes.
Patch by Xiaoyi Guo!
This also fixes an unsupported dbg.value test case. Codegen was
previously incorrect but the test was passing by luck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182885 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Hexagon')
| -rw-r--r-- | lib/Target/Hexagon/HexagonISelLowering.cpp | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/lib/Target/Hexagon/HexagonISelLowering.cpp b/lib/Target/Hexagon/HexagonISelLowering.cpp index e1d5592..2b0fa5e 100644 --- a/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -513,7 +513,8 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, if (!isTailCall) Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes, - getPointerTy(), true)); + getPointerTy(), true), + dl); // Build a sequence of copy-to-reg nodes chained together with token // chain and flag operands which copy the outgoing args into registers. @@ -588,7 +589,7 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, // Create the CALLSEQ_END node. Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), - DAG.getIntPtrConstant(0, true), InFlag); + DAG.getIntPtrConstant(0, true), InFlag, dl); InFlag = Chain.getValue(1); // Handle result values, copying them out of physregs into vregs that we |