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| author | Juergen Ributzka <juergen@apple.com> | 2013-11-13 01:57:54 +0000 |
|---|---|---|
| committer | Juergen Ributzka <juergen@apple.com> | 2013-11-13 01:57:54 +0000 |
| commit | c7e77f91fecd662b198939a9a8ee0a0cc3828fc4 (patch) | |
| tree | 10b8c447404b770e3ab436452f5fedafebedc151 /lib/Target/Hexagon | |
| parent | cfe36cb02a4c2d99fd2ea0892e7b2668f2df2b8b (diff) | |
| download | external_llvm-c7e77f91fecd662b198939a9a8ee0a0cc3828fc4.zip external_llvm-c7e77f91fecd662b198939a9a8ee0a0cc3828fc4.tar.gz external_llvm-c7e77f91fecd662b198939a9a8ee0a0cc3828fc4.tar.bz2 | |
SelectionDAG: Teach the legalizer to split SETCC if VSELECT needs splitting too.
This patch reapplies r193676 with an additional fix for the Hexagon backend. The
SystemZ backend has already been fixed by r194148.
The Type Legalizer recognizes that VSELECT needs to be split, because the type
is to wide for the given target. The same does not always apply to SETCC,
because less space is required to encode the result of a comparison. As a result
VSELECT is split and SETCC is unrolled into scalar comparisons.
This commit fixes the issue by checking for VSELECT-SETCC patterns in the DAG
Combiner. If a matching pattern is found, then the result mask of SETCC is
promoted to the expected vector mask type for the given target. Now the type
legalizer will split both VSELECT and SETCC.
This allows the following X86 DAG Combine code to sucessfully detect the MIN/MAX
pattern. This fixes PR16695, PR17002, and <rdar://problem/14594431>.
Reviewed by Nadav
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194542 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Hexagon')
| -rw-r--r-- | lib/Target/Hexagon/HexagonISelLowering.h | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/lib/Target/Hexagon/HexagonISelLowering.h b/lib/Target/Hexagon/HexagonISelLowering.h index 4fe0107..73da226 100644 --- a/lib/Target/Hexagon/HexagonISelLowering.h +++ b/lib/Target/Hexagon/HexagonISelLowering.h @@ -141,8 +141,11 @@ namespace llvm { SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; - virtual EVT getSetCCResultType(LLVMContext &, EVT) const { - return MVT::i1; + virtual EVT getSetCCResultType(LLVMContext &C, EVT VT) const { + if (!VT.isVector()) + return MVT::i1; + else + return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements()); } virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, |