Efficient pattern for store truncate. Patch by Evandro Menezes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151166 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 7 insertions, 22 deletions

diff --git a/lib/Target/Hexagon/HexagonAsmPrinter.cpp b/lib/Target/Hexagon/HexagonAsmPrinter.cpp
index 1de9af2..9725449 100644
--- a/lib/Target/Hexagon/HexagonAsmPrinter.cpp
+++ b/lib/Target/Hexagon/HexagonAsmPrinter.cpp
@@ -374,19 +374,6 @@ void HexagonAsmPrinter::EmitInstruction(const MachineInstr *MI) {
     O << "}";
     }
     printInstruction(MI, O);
-  } else if (MI->getOpcode() == Hexagon::STriwt) {
-    //
-    // Handle truncated store on Hexagon.
-    //
-    O << "\tmemw(";
-    printHexagonMEMriOperand(MI, 0, O);
-
-    O << ") = ";
-    unsigned SubRegNum =
-      TM.getRegisterInfo()->getSubReg(MI->getOperand(2)
-                                      .getReg(), Hexagon::subreg_loreg);
-    const char *SubRegName = getRegisterName(SubRegNum);
-    O << SubRegName << '\n';
   } else if (MI->getOpcode() == Hexagon::MPYI_rin) {
     // Handle multipy with -ve constant on Hexagon:
     // "$dst =- mpyi($src1, #$src2)"
diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp
index 9c830d0..07872d4 100644
--- a/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -1397,7 +1397,6 @@ isValidOffset(const int Opcode, const int Offset) const {
 
   case Hexagon::LDriw:
   case Hexagon::STriw:
-  case Hexagon::STriwt:
     assert((Offset % 4 == 0) && "Offset has incorrect alignment");
     return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
       (Offset <= Hexagon_MEMW_OFFSET_MAX);
diff --git a/lib/Target/Hexagon/HexagonInstrInfo.td b/lib/Target/Hexagon/HexagonInstrInfo.td
index da8c548..f3c6622 100644
--- a/lib/Target/Hexagon/HexagonInstrInfo.td
+++ b/lib/Target/Hexagon/HexagonInstrInfo.td
@@ -1999,11 +1999,6 @@ def STriw_indexed : STInst<(outs),
             "memw($src1+#$src2) = $src3",
             [(store IntRegs:$src3, (add IntRegs:$src1, s11_2ImmPred:$src2))]>;
 
-def STriwt : STInst<(outs),
-            (ins MEMri:$addr, DoubleRegs:$src1),
-            "memw($addr) = $src1",
-            [(truncstorei32 DoubleRegs:$src1, ADDRriS11_2:$addr)]>;
-
 let mayStore = 1, neverHasSideEffects = 1 in
 def STriw_GP : STInst<(outs),
             (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
@@ -2745,7 +2740,7 @@ def : Pat<(i32 (trunc DoubleRegs:$src)),
 def :  Pat<(i1 (trunc DoubleRegs:$src)),
        (i1 (TFR_PdRs (i32(EXTRACT_SUBREG DoubleRegs:$src, subreg_loreg))))>;
 
-// Map memw(Rs) = Rdd -> memw(Rs) = Rt.
+// Map memb(Rs) = Rdd -> memb(Rs) = Rt.
 def : Pat<(truncstorei8 DoubleRegs:$src, ADDRriS11_0:$addr),
       (STrib ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG DoubleRegs:$src,
                                                      subreg_loreg)))>;
@@ -2755,6 +2750,11 @@ def : Pat<(truncstorei16 DoubleRegs:$src, ADDRriS11_0:$addr),
       (STrih ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG DoubleRegs:$src,
                                                      subreg_loreg)))>;
 
+// Map memw(Rs) = Rdd -> memw(Rs) = Rt.
+def : Pat<(truncstorei32 DoubleRegs:$src, ADDRriS11_0:$addr),
+      (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG DoubleRegs:$src,
+                                                     subreg_loreg)))>;
+
 // Map from i1 = constant<-1>; memw(addr) = i1 -> r0 = 1; memw(addr) = r0.
 def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
       (STrib ADDRriS11_2:$addr, (TFRI 1))>;
diff --git a/lib/Target/Hexagon/HexagonRegisterInfo.cpp b/lib/Target/Hexagon/HexagonRegisterInfo.cpp
index d776c09..4eacf01 100644
--- a/lib/Target/Hexagon/HexagonRegisterInfo.cpp
+++ b/lib/Target/Hexagon/HexagonRegisterInfo.cpp
@@ -206,8 +206,7 @@ void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
       } else if ((MI.getOpcode() == Hexagon::STriw) ||
                  (MI.getOpcode() == Hexagon::STrid) ||
                  (MI.getOpcode() == Hexagon::STrih) ||
-                 (MI.getOpcode() == Hexagon::STrib) ||
-                 (MI.getOpcode() == Hexagon::STriwt)) {
+                 (MI.getOpcode() == Hexagon::STrib)) {
         // For stores, we need a reserved register. Change
         // memw(r30 + #10000) = r0 to:
         //