Change instruction description to split OperandList into OutOperandList and

InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 16 insertions, 15 deletions

diff --git a/lib/Target/IA64/IA64InstrFormats.td b/lib/Target/IA64/IA64InstrFormats.td
index ba6c574..f16109b 100644
--- a/lib/Target/IA64/IA64InstrFormats.td
+++ b/lib/Target/IA64/IA64InstrFormats.td
@@ -16,11 +16,12 @@
 // Instruction format superclass
 //===----------------------------------------------------------------------===//
 
-class InstIA64<bits<4> op, dag OL, string asmstr> : Instruction { 
+class InstIA64<bits<4> op, dag OOL, dag IOL, string asmstr> : Instruction { 
   // IA64 instruction baseline
   field bits<41> Inst;
   let Namespace = "IA64";
-  let OperandList = OL;
+  let OutOperandList = OOL;
+  let InOperandList = IOL;
   let AsmString = asmstr;
 
   let Inst{40-37} = op;
@@ -30,30 +31,30 @@ class InstIA64<bits<4> op, dag OL, string asmstr> : Instruction {
 //We should have:
 // A, I, M, F, B, L+X
 
-class AForm<bits<4> opcode, bits<6> qpReg, dag OL, string asmstr> : 
-  InstIA64<opcode, OL, asmstr> {
+class AForm<bits<4> opcode, bits<6> qpReg, dag OOL, dag IOL, string asmstr> : 
+  InstIA64<opcode, OOL, IOL, asmstr> {
 
   let Inst{5-0} = qpReg;
 }
 
-class AForm_DAG<bits<4> opcode, bits<6> qpReg, dag OL, string asmstr,
+class AForm_DAG<bits<4> opcode, bits<6> qpReg, dag OOL, dag IOL, string asmstr,
       list<dag> pattern> : 
-  InstIA64<opcode, OL, asmstr> {
+  InstIA64<opcode, OOL, IOL, asmstr> {
 
   let Pattern = pattern;
   let Inst{5-0} = qpReg;
 }
 
 let isBranch = 1, isTerminator = 1 in
-class BForm<bits<4> opcode, bits<6> x6, bits<3> btype, dag OL, string asmstr> :
-  InstIA64<opcode, OL, asmstr> {
+class BForm<bits<4> opcode, bits<6> x6, bits<3> btype, dag OOL, dag IOL, string asmstr> :
+  InstIA64<opcode, OOL, IOL, asmstr> {
 
   let Inst{32-27} = x6;
   let Inst{8-6} = btype;
 }
 
-class MForm<bits<4> opcode, bits<6> x6, dag OL, string asmstr> :
-  InstIA64<opcode, OL, asmstr> {
+class MForm<bits<4> opcode, bits<6> x6, dag OOL, dag IOL, string asmstr> :
+  InstIA64<opcode, OOL, IOL, asmstr> {
     bits<7> Ra;
     bits<7> Rb;
     bits<16> disp;
@@ -63,17 +64,17 @@ class MForm<bits<4> opcode, bits<6> x6, dag OL, string asmstr> :
     let Inst{15-0} = disp;
 }
 
-class RawForm<bits<4> opcode, bits<26> rest, dag OL, string asmstr> :
-  InstIA64<opcode, OL, asmstr> {
+class RawForm<bits<4> opcode, bits<26> rest, dag OOL, dag IOL, string asmstr> :
+  InstIA64<opcode, OOL, IOL, asmstr> {
     let Inst{25-0} = rest;
 }
 
 // Pseudo instructions.
-class PseudoInstIA64<dag OL, string nm> : InstIA64<0, OL, nm>  {
+class PseudoInstIA64<dag OOL, dag IOL, string nm> : InstIA64<0, OOL, IOL, nm>  {
 }
 
-class PseudoInstIA64_DAG<dag OL, string nm, list<dag> pattern>
-  : InstIA64<0, OL, nm> {
+class PseudoInstIA64_DAG<dag OOL, dag IOL, string nm, list<dag> pattern>
+  : InstIA64<0, OOL, IOL, nm> {
   let Pattern = pattern;
 }