Change instruction description to split OperandList into OutOperandList and

InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 174 insertions, 173 deletions

diff --git a/lib/Target/IA64/IA64InstrFormats.td b/lib/Target/IA64/IA64InstrFormats.td
index ba6c574..f16109b 100644
--- a/lib/Target/IA64/IA64InstrFormats.td
+++ b/lib/Target/IA64/IA64InstrFormats.td
@@ -16,11 +16,12 @@
 // Instruction format superclass
 //===----------------------------------------------------------------------===//
 
-class InstIA64<bits<4> op, dag OL, string asmstr> : Instruction { 
+class InstIA64<bits<4> op, dag OOL, dag IOL, string asmstr> : Instruction { 
   // IA64 instruction baseline
   field bits<41> Inst;
   let Namespace = "IA64";
-  let OperandList = OL;
+  let OutOperandList = OOL;
+  let InOperandList = IOL;
   let AsmString = asmstr;
 
   let Inst{40-37} = op;
@@ -30,30 +31,30 @@ class InstIA64<bits<4> op, dag OL, string asmstr> : Instruction {
 //We should have:
 // A, I, M, F, B, L+X
 
-class AForm<bits<4> opcode, bits<6> qpReg, dag OL, string asmstr> : 
-  InstIA64<opcode, OL, asmstr> {
+class AForm<bits<4> opcode, bits<6> qpReg, dag OOL, dag IOL, string asmstr> : 
+  InstIA64<opcode, OOL, IOL, asmstr> {
 
   let Inst{5-0} = qpReg;
 }
 
-class AForm_DAG<bits<4> opcode, bits<6> qpReg, dag OL, string asmstr,
+class AForm_DAG<bits<4> opcode, bits<6> qpReg, dag OOL, dag IOL, string asmstr,
       list<dag> pattern> : 
-  InstIA64<opcode, OL, asmstr> {
+  InstIA64<opcode, OOL, IOL, asmstr> {
 
   let Pattern = pattern;
   let Inst{5-0} = qpReg;
 }
 
 let isBranch = 1, isTerminator = 1 in
-class BForm<bits<4> opcode, bits<6> x6, bits<3> btype, dag OL, string asmstr> :
-  InstIA64<opcode, OL, asmstr> {
+class BForm<bits<4> opcode, bits<6> x6, bits<3> btype, dag OOL, dag IOL, string asmstr> :
+  InstIA64<opcode, OOL, IOL, asmstr> {
 
   let Inst{32-27} = x6;
   let Inst{8-6} = btype;
 }
 
-class MForm<bits<4> opcode, bits<6> x6, dag OL, string asmstr> :
-  InstIA64<opcode, OL, asmstr> {
+class MForm<bits<4> opcode, bits<6> x6, dag OOL, dag IOL, string asmstr> :
+  InstIA64<opcode, OOL, IOL, asmstr> {
     bits<7> Ra;
     bits<7> Rb;
     bits<16> disp;
@@ -63,17 +64,17 @@ class MForm<bits<4> opcode, bits<6> x6, dag OL, string asmstr> :
     let Inst{15-0} = disp;
 }
 
-class RawForm<bits<4> opcode, bits<26> rest, dag OL, string asmstr> :
-  InstIA64<opcode, OL, asmstr> {
+class RawForm<bits<4> opcode, bits<26> rest, dag OOL, dag IOL, string asmstr> :
+  InstIA64<opcode, OOL, IOL, asmstr> {
     let Inst{25-0} = rest;
 }
 
 // Pseudo instructions.
-class PseudoInstIA64<dag OL, string nm> : InstIA64<0, OL, nm>  {
+class PseudoInstIA64<dag OOL, dag IOL, string nm> : InstIA64<0, OOL, IOL, nm>  {
 }
 
-class PseudoInstIA64_DAG<dag OL, string nm, list<dag> pattern>
-  : InstIA64<0, OL, nm> {
+class PseudoInstIA64_DAG<dag OOL, dag IOL, string nm, list<dag> pattern>
+  : InstIA64<0, OOL, IOL, nm> {
   let Pattern = pattern;
 }
 
diff --git a/lib/Target/IA64/IA64InstrInfo.td b/lib/Target/IA64/IA64InstrInfo.td
index 57f5f66..536e617 100644
--- a/lib/Target/IA64/IA64InstrInfo.td
+++ b/lib/Target/IA64/IA64InstrInfo.td
@@ -113,49 +113,49 @@ def immSExt14  : PatLeaf<(i64 imm), [{
 // field - i.e., true. used to keep movl happy
 def imm64  : PatLeaf<(i64 imm)>; 
 
-def ADD  : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
+def ADD  : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
            "add $dst = $src1, $src2",
 	   [(set GR:$dst, (add GR:$src1, GR:$src2))]>, isA;
 
-def ADD1 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
+def ADD1 : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
            "add $dst = $src1, $src2, 1",
 	   [(set GR:$dst, (add (add GR:$src1, GR:$src2), 1))]>, isA;
 
-def ADDS : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, s14imm:$imm),
+def ADDS : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, s14imm:$imm),
            "adds $dst = $imm, $src1",
 	   [(set GR:$dst, (add GR:$src1, immSExt14:$imm))]>, isA;
  
-def MOVL : AForm_DAG<0x03, 0x0b, (ops GR:$dst, s64imm:$imm),
+def MOVL : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins s64imm:$imm),
            "movl $dst = $imm",
 	   [(set GR:$dst, imm64:$imm)]>, isLX;
 
-def ADDL_GA : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, globaladdress:$imm),
+def ADDL_GA : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, globaladdress:$imm),
            "addl $dst = $imm, $src1",
 	   []>, isA;
 
 // hmm 
-def ADDL_EA : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, calltarget:$imm),
+def ADDL_EA : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, calltarget:$imm),
            "addl $dst = $imm, $src1",
 	   []>, isA;
  
-def SUB  : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
+def SUB  : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
            "sub $dst = $src1, $src2",
 	   [(set GR:$dst, (sub GR:$src1, GR:$src2))]>, isA;
 
-def SUB1 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
+def SUB1 : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
            "sub $dst = $src1, $src2, 1",
 	   [(set GR:$dst, (add (sub GR: $src1, GR:$src2), -1))]>, isA;
 
 let isTwoAddress = 1 in {
 def TPCADDIMM22 : AForm<0x03, 0x0b,
-  (ops GR:$dst, GR:$src1, s22imm:$imm, PR:$qp),
+  (outs GR:$dst), (ins GR:$src1, s22imm:$imm, PR:$qp),
     "($qp) add $dst = $imm, $dst">, isA;
 def TPCADDS : AForm_DAG<0x03, 0x0b,
-  (ops GR:$dst, GR:$src1, s14imm:$imm, PR:$qp),
+  (outs GR:$dst), (ins GR:$src1, s14imm:$imm, PR:$qp),
     "($qp) adds $dst = $imm, $dst",
     []>, isA;
 def TPCMPIMM8NE : AForm<0x03, 0x0b,
-  (ops PR:$dst, PR:$src1, s22imm:$imm, GR:$src2, PR:$qp),
+  (outs PR:$dst), (ins PR:$src1, s22imm:$imm, GR:$src2, PR:$qp),
     "($qp) cmp.ne $dst , p0 = $imm, $src2">, isA;
 }
 
@@ -166,65 +166,65 @@ def AXTb : Pat<(anyext PR:$src),
           (TPCADDIMM22 (ADDS r0, 0), 1, PR:$src)>; 
 
 // normal sign/zero-extends
-def SXT1 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt1 $dst = $src",
+def SXT1 : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src), "sxt1 $dst = $src",
            [(set GR:$dst, (sext_inreg GR:$src, i8))]>, isI;
-def ZXT1 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt1 $dst = $src",
+def ZXT1 : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src), "zxt1 $dst = $src",
            [(set GR:$dst, (and GR:$src, 255))]>, isI;
-def SXT2 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt2 $dst = $src",
+def SXT2 : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src), "sxt2 $dst = $src",
            [(set GR:$dst, (sext_inreg GR:$src, i16))]>, isI;
-def ZXT2 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt2 $dst = $src",
+def ZXT2 : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src), "zxt2 $dst = $src",
            [(set GR:$dst, (and GR:$src, 65535))]>, isI;
-def SXT4 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt4 $dst = $src",
+def SXT4 : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src), "sxt4 $dst = $src",
            [(set GR:$dst, (sext_inreg GR:$src, i32))]>, isI;
-def ZXT4 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt4 $dst = $src",
+def ZXT4 : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src), "zxt4 $dst = $src",
            [(set GR:$dst, (and GR:$src, is32ones))]>, isI;
 
 // fixme: shrs vs shru?
-def MIX1L : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
+def MIX1L : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
           "mix1.l $dst = $src1, $src2",
 	  [(set GR:$dst, (or (and GR:$src1, isMIX1Lable),
 	                     (and (srl GR:$src2, (i64 8)), isMIX1Lable)))]>, isI;
 
-def MIX2L : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
+def MIX2L : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
           "mix2.l $dst = $src1, $src2",
 	  [(set GR:$dst, (or (and GR:$src1, isMIX2Lable),
 	                     (and (srl GR:$src2, (i64 16)), isMIX2Lable)))]>, isI;
 
-def MIX4L : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
+def MIX4L : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
           "mix4.l $dst = $src1, $src2",
 	  [(set GR:$dst, (or (and GR:$src1, isMIX4Lable),
 	                     (and (srl GR:$src2, (i64 32)), isMIX4Lable)))]>, isI;
 
-def MIX1R : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
+def MIX1R : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
           "mix1.r $dst = $src1, $src2",
 	  [(set GR:$dst, (or (and (shl GR:$src1, (i64 8)), isMIX1Rable),
 	                     (and GR:$src2, isMIX1Rable)))]>, isI;
 
-def MIX2R : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
+def MIX2R : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
           "mix2.r $dst = $src1, $src2",
 	  [(set GR:$dst, (or (and (shl GR:$src1, (i64 16)), isMIX2Rable),
 	                     (and GR:$src2, isMIX2Rable)))]>, isI;
 
-def MIX4R : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
+def MIX4R : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
           "mix4.r $dst = $src1, $src2",
 	  [(set GR:$dst, (or (and (shl GR:$src1, (i64 32)), isMIX4Rable),
 	                     (and GR:$src2, isMIX4Rable)))]>, isI;
 
-def GETFSIGD : AForm_DAG<0x03, 0x0b, (ops GR:$dst, FP:$src),
+def GETFSIGD : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins FP:$src),
   "getf.sig $dst = $src",
   []>, isM;
 
-def SETFSIGD : AForm_DAG<0x03, 0x0b, (ops FP:$dst, GR:$src),
+def SETFSIGD : AForm_DAG<0x03, 0x0b, (outs FP:$dst), (ins GR:$src),
   "setf.sig $dst = $src",
   []>, isM;
 
-def XMALD : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
+def XMALD : AForm_DAG<0x03, 0x0b, (outs FP:$dst), (ins FP:$src1, FP:$src2, FP:$src3),
   "xma.l $dst = $src1, $src2, $src3",
   []>, isF;
-def XMAHD : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
+def XMAHD : AForm_DAG<0x03, 0x0b, (outs FP:$dst), (ins FP:$src1, FP:$src2, FP:$src3),
   "xma.h $dst = $src1, $src2, $src3",
   []>, isF;
-def XMAHUD : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
+def XMAHUD : AForm_DAG<0x03, 0x0b, (outs FP:$dst), (ins FP:$src1, FP:$src2, FP:$src3),
   "xma.hu $dst = $src1, $src2, $src3",
   []>, isF;
 
@@ -239,98 +239,98 @@ def : Pat<(mulhu GR:$src1, GR:$src2),
 // TODO: addp4 (addp4 dst = src, r0 is a 32-bit add)
 // has imm form, too
 
-// def ADDS : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s14imm:$imm),
+// def ADDS : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, s14imm:$imm),
 //   "adds $dst = $imm, $src1">;
 
-def AND   : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
+def AND   : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
           "and $dst = $src1, $src2",
 	  [(set GR:$dst, (and GR:$src1, GR:$src2))]>, isA;
-def ANDCM : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
+def ANDCM : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
           "andcm $dst = $src1, $src2",
 	  [(set GR:$dst, (and GR:$src1, (not GR:$src2)))]>, isA;
 // TODO: and/andcm/or/xor/add/sub/shift immediate forms
-def OR    : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
+def OR    : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
           "or $dst = $src1, $src2",
 	  [(set GR:$dst, (or GR:$src1, GR:$src2))]>, isA;
 
-def pOR   : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2, PR:$qp),
+def pOR   : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2, PR:$qp),
           "($qp) or $dst = $src1, $src2">, isA;
 
 // the following are all a bit unfortunate: we throw away the complement
 // of the compare!
-def CMPEQ : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
+def CMPEQ : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2),
           "cmp.eq $dst, p0 = $src1, $src2",
 	  [(set PR:$dst, (seteq GR:$src1, GR:$src2))]>, isA;
-def CMPGT : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
+def CMPGT : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2),
           "cmp.gt $dst, p0 = $src1, $src2",
 	  [(set PR:$dst, (setgt GR:$src1, GR:$src2))]>, isA;
-def CMPGE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
+def CMPGE : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2),
           "cmp.ge $dst, p0 = $src1, $src2",
 	  [(set PR:$dst, (setge GR:$src1, GR:$src2))]>, isA;
-def CMPLT : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
+def CMPLT : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2),
           "cmp.lt $dst, p0 = $src1, $src2",
 	  [(set PR:$dst, (setlt GR:$src1, GR:$src2))]>, isA;
-def CMPLE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
+def CMPLE : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2),
           "cmp.le $dst, p0 = $src1, $src2",
 	  [(set PR:$dst, (setle GR:$src1, GR:$src2))]>, isA;
-def CMPNE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
+def CMPNE : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2),
           "cmp.ne $dst, p0 = $src1, $src2",
 	  [(set PR:$dst, (setne GR:$src1, GR:$src2))]>, isA;
-def CMPLTU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
+def CMPLTU: AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2),
           "cmp.ltu $dst, p0 = $src1, $src2",
 	  [(set PR:$dst, (setult GR:$src1, GR:$src2))]>, isA;
-def CMPGTU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
+def CMPGTU: AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2),
           "cmp.gtu $dst, p0 = $src1, $src2",
 	  [(set PR:$dst, (setugt GR:$src1, GR:$src2))]>, isA;
-def CMPLEU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
+def CMPLEU: AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2),
           "cmp.leu $dst, p0 = $src1, $src2",
 	  [(set PR:$dst, (setule GR:$src1, GR:$src2))]>, isA;
-def CMPGEU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
+def CMPGEU: AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2),
           "cmp.geu $dst, p0 = $src1, $src2",
 	  [(set PR:$dst, (setuge GR:$src1, GR:$src2))]>, isA;
 
 // and we do the whole thing again for FP compares!
-def FCMPEQ : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
+def FCMPEQ : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2),
           "fcmp.eq $dst, p0 = $src1, $src2",
           [(set PR:$dst, (seteq FP:$src1, FP:$src2))]>, isF;
-def FCMPGT : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
+def FCMPGT : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2),
           "fcmp.gt $dst, p0 = $src1, $src2",
 	  [(set PR:$dst, (setgt FP:$src1, FP:$src2))]>, isF;
-def FCMPGE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
+def FCMPGE : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2),
           "fcmp.ge $dst, p0 = $src1, $src2",
 	  [(set PR:$dst, (setge FP:$src1, FP:$src2))]>, isF;
-def FCMPLT : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
+def FCMPLT : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2),
           "fcmp.lt $dst, p0 = $src1, $src2",
 	  [(set PR:$dst, (setlt FP:$src1, FP:$src2))]>, isF;
-def FCMPLE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
+def FCMPLE : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2),
           "fcmp.le $dst, p0 = $src1, $src2",
 	  [(set PR:$dst, (setle FP:$src1, FP:$src2))]>, isF;
-def FCMPNE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
+def FCMPNE : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2),
           "fcmp.neq $dst, p0 = $src1, $src2",
 	  [(set PR:$dst, (setne FP:$src1, FP:$src2))]>, isF;
-def FCMPLTU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
+def FCMPLTU: AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2),
           "fcmp.lt $dst, p0 = $src1, $src2",
 	  [(set PR:$dst, (setult FP:$src1, FP:$src2))]>, isF;
-def FCMPGTU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
+def FCMPGTU: AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2),
           "fcmp.gt $dst, p0 = $src1, $src2",
 	  [(set PR:$dst, (setugt FP:$src1, FP:$src2))]>, isF;
-def FCMPLEU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
+def FCMPLEU: AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2),
           "fcmp.le $dst, p0 = $src1, $src2",
 	  [(set PR:$dst, (setule FP:$src1, FP:$src2))]>, isF;
-def FCMPGEU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
+def FCMPGEU: AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2),
           "fcmp.ge $dst, p0 = $src1, $src2",
 	  [(set PR:$dst, (setuge FP:$src1, FP:$src2))]>, isF;
 
-def PCMPEQUNCR0R0 : AForm<0x03, 0x0b, (ops PR:$dst, PR:$qp),
+def PCMPEQUNCR0R0 : AForm<0x03, 0x0b, (outs PR:$dst), (ins PR:$qp),
     "($qp) cmp.eq.unc $dst, p0 = r0, r0">, isA;
 
 def : Pat<(trunc GR:$src),  // truncate i64 to i1
           (CMPNE GR:$src, r0)>; // $src!=0? If so, PR:$dst=true
 	  
 let isTwoAddress=1 in {
-  def TPCMPEQR0R0 : AForm<0x03, 0x0b, (ops PR:$dst, PR:$bogus, PR:$qp),
+  def TPCMPEQR0R0 : AForm<0x03, 0x0b, (outs PR:$dst), (ins PR:$bogus, PR:$qp),
     "($qp) cmp.eq $dst, p0 = r0, r0">, isA;
-  def TPCMPNER0R0 : AForm<0x03, 0x0b, (ops PR:$dst, PR:$bogus, PR:$qp),
+  def TPCMPNER0R0 : AForm<0x03, 0x0b, (outs PR:$dst), (ins PR:$bogus, PR:$qp),
     "($qp) cmp.ne $dst, p0 = r0, r0">, isA;
 }
 
@@ -394,47 +394,47 @@ def bXOR  : Pat<(xor PR:$src1, PR:$src2),
 	               (TPCADDS (ADDS r0, 0), 1, PR:$src2),
                         PR:$src1)>;
 
-def XOR   : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
+def XOR   : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
           "xor $dst = $src1, $src2",
 	  [(set GR:$dst, (xor GR:$src1, GR:$src2))]>, isA;
 
-def SHLADD: AForm_DAG<0x03, 0x0b, (ops GR:$dst,GR:$src1,s64imm:$imm,GR:$src2),
+def SHLADD: AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1,s64imm:$imm,GR:$src2),
           "shladd $dst = $src1, $imm, $src2",
           [(set GR:$dst, (add GR:$src2, (shl GR:$src1, isSHLADDimm:$imm)))]>, isA;
 
-def SHL   : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
+def SHL   : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
           "shl $dst = $src1, $src2",
 	  [(set GR:$dst, (shl GR:$src1, GR:$src2))]>, isI;
 
-def SHRU  : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
+def SHRU  : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
           "shr.u $dst = $src1, $src2",
 	  [(set GR:$dst, (srl GR:$src1, GR:$src2))]>, isI;
 
-def SHRS  : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
+def SHRS  : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
           "shr $dst = $src1, $src2",
 	  [(set GR:$dst, (sra GR:$src1, GR:$src2))]>, isI;
 
-def MOV : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "mov $dst = $src">, isA;
-def FMOV : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
+def MOV : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$src), "mov $dst = $src">, isA;
+def FMOV : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src),
   "mov $dst = $src">, isF; // XXX: there _is_ no fmov
-def PMOV : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src, PR:$qp),
+def PMOV : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$src, PR:$qp),
   "($qp) mov $dst = $src">, isA;
 
-def SPILL_ALL_PREDICATES_TO_GR : AForm<0x03, 0x0b, (ops GR:$dst),
+def SPILL_ALL_PREDICATES_TO_GR : AForm<0x03, 0x0b, (outs GR:$dst), (ins),
   "mov $dst = pr">, isI;
-def FILL_ALL_PREDICATES_FROM_GR : AForm<0x03, 0x0b, (ops GR:$src),
+def FILL_ALL_PREDICATES_FROM_GR : AForm<0x03, 0x0b, (outs), (ins GR:$src),
   "mov pr = $src">, isI;
 
 let isTwoAddress = 1 in {
-  def CMOV : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src2, GR:$src, PR:$qp),
+  def CMOV : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$src2, GR:$src, PR:$qp),
     "($qp) mov $dst = $src">, isA;
 }
 
-def PFMOV : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src, PR:$qp),
+def PFMOV : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src, PR:$qp),
   "($qp) mov $dst = $src">, isF;
 
 let isTwoAddress = 1 in {
-  def CFMOV : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src2, FP:$src, PR:$qp),
+  def CFMOV : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src2, FP:$src, PR:$qp),
     "($qp) mov $dst = $src">, isF;
 }
 
@@ -457,223 +457,223 @@ def : Pat<(i1  0), (CMPNE r0, r0)>; // TODO: any instruction actually *using*
 // TODO: support postincrement (reg, imm9) loads+stores - this needs more
 // tablegen support
 
-def IDEF : PseudoInstIA64<(ops variable_ops), "// IDEF">;
+def IDEF : PseudoInstIA64<(outs variable_ops), (ins), "// IDEF">;
 
-def IDEF_GR_D : PseudoInstIA64_DAG<(ops GR:$reg), "// $reg = IDEF",
+def IDEF_GR_D : PseudoInstIA64_DAG<(outs GR:$reg), (ins), "// $reg = IDEF",
     [(set GR:$reg, (undef))]>;
-def IDEF_FP_D : PseudoInstIA64_DAG<(ops FP:$reg), "// $reg = IDEF",
+def IDEF_FP_D : PseudoInstIA64_DAG<(outs FP:$reg), (ins), "// $reg = IDEF",
     [(set FP:$reg, (undef))]>;
-def IDEF_PR_D : PseudoInstIA64_DAG<(ops PR:$reg), "// $reg = IDEF",
+def IDEF_PR_D : PseudoInstIA64_DAG<(outs PR:$reg), (ins), "// $reg = IDEF",
     [(set PR:$reg, (undef))]>;
 
-def IUSE : PseudoInstIA64<(ops variable_ops), "// IUSE">;
-def ADJUSTCALLSTACKUP : PseudoInstIA64<(ops variable_ops),
+def IUSE : PseudoInstIA64<(outs), (ins variable_ops), "// IUSE">;
+def ADJUSTCALLSTACKUP : PseudoInstIA64<(outs), (ins variable_ops),
                                         "// ADJUSTCALLSTACKUP">;
-def ADJUSTCALLSTACKDOWN : PseudoInstIA64<(ops variable_ops),
+def ADJUSTCALLSTACKDOWN : PseudoInstIA64<(outs), (ins variable_ops),
                                          "// ADJUSTCALLSTACKDOWN">;
-def PSEUDO_ALLOC : PseudoInstIA64<(ops GR:$foo), "// PSEUDO_ALLOC">;
+def PSEUDO_ALLOC : PseudoInstIA64<(outs), (ins GR:$foo), "// PSEUDO_ALLOC">;
 
 def ALLOC : AForm<0x03, 0x0b,
-  (ops GR:$dst, i8imm:$inputs, i8imm:$locals, i8imm:$outputs, i8imm:$rotating),
+  (outs GR:$dst), (ins i8imm:$inputs, i8imm:$locals, i8imm:$outputs, i8imm:$rotating),
     "alloc $dst = ar.pfs,$inputs,$locals,$outputs,$rotating">, isM;
 
 let isTwoAddress = 1 in {
   def TCMPNE : AForm<0x03, 0x0b,
-  (ops PR:$dst, PR:$src2, GR:$src3, GR:$src4),
+  (outs PR:$dst), (ins PR:$src2, GR:$src3, GR:$src4),
     "cmp.ne $dst, p0 = $src3, $src4">, isA;
   
   def TPCMPEQOR : AForm<0x03, 0x0b,
-  (ops PR:$dst, PR:$src2, GR:$src3, GR:$src4, PR:$qp),
+  (outs PR:$dst), (ins PR:$src2, GR:$src3, GR:$src4, PR:$qp),
     "($qp) cmp.eq.or $dst, p0 = $src3, $src4">, isA;
   
   def TPCMPNE : AForm<0x03, 0x0b,
-  (ops PR:$dst, PR:$src2, GR:$src3, GR:$src4, PR:$qp),
+  (outs PR:$dst), (ins PR:$src2, GR:$src3, GR:$src4, PR:$qp),
     "($qp) cmp.ne $dst, p0 = $src3, $src4">, isA;
   
   def TPCMPEQ : AForm<0x03, 0x0b,
-  (ops PR:$dst, PR:$src2, GR:$src3, GR:$src4, PR:$qp),
+  (outs PR:$dst), (ins PR:$src2, GR:$src3, GR:$src4, PR:$qp),
     "($qp) cmp.eq $dst, p0 = $src3, $src4">, isA;
 }
 
-def MOVSIMM14 : AForm<0x03, 0x0b, (ops GR:$dst, s14imm:$imm),
+def MOVSIMM14 : AForm<0x03, 0x0b, (outs GR:$dst), (ins s14imm:$imm),
   "mov $dst = $imm">, isA;
-def MOVSIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, s22imm:$imm),
+def MOVSIMM22 : AForm<0x03, 0x0b, (outs GR:$dst), (ins s22imm:$imm),
   "mov $dst = $imm">, isA;
-def MOVLIMM64 : AForm<0x03, 0x0b, (ops GR:$dst, s64imm:$imm),
+def MOVLIMM64 : AForm<0x03, 0x0b, (outs GR:$dst), (ins s64imm:$imm),
   "movl $dst = $imm">, isLX;
 
-def SHLI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm), 
+def SHLI : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, u6imm:$imm), 
   "shl $dst = $src1, $imm">, isI;
-def SHRUI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm),
+def SHRUI : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, u6imm:$imm),
   "shr.u $dst = $src1, $imm">, isI;
-def SHRSI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm),
+def SHRSI : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, u6imm:$imm),
   "shr $dst = $src1, $imm">, isI;
 
 def EXTRU : AForm<0x03, 0x0b,
-  (ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2),
+  (outs GR:$dst), (ins GR:$src1, u6imm:$imm1, u6imm:$imm2),
   "extr.u $dst = $src1, $imm1, $imm2">, isI;
 
 def DEPZ : AForm<0x03, 0x0b,
-  (ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2),
+  (outs GR:$dst), (ins GR:$src1, u6imm:$imm1, u6imm:$imm2),
   "dep.z $dst = $src1, $imm1, $imm2">, isI;
 
-def PCMPEQOR : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2, PR:$qp),
+def PCMPEQOR : AForm<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2, PR:$qp),
   "($qp) cmp.eq.or $dst, p0 = $src1, $src2">, isA;
-def PCMPEQUNC : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2, PR:$qp),
+def PCMPEQUNC : AForm<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2, PR:$qp),
   "($qp) cmp.eq.unc $dst, p0 = $src1, $src2">, isA;
-def PCMPNE : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2, PR:$qp),
+def PCMPNE : AForm<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2, PR:$qp),
   "($qp) cmp.ne $dst, p0 = $src1, $src2">, isA;
 
 // two destinations! 
-def BCMPEQ : AForm<0x03, 0x0b, (ops PR:$dst1, PR:$dst2, GR:$src1, GR:$src2),
+def BCMPEQ : AForm<0x03, 0x0b, (outs PR:$dst1, PR:$dst2), (ins GR:$src1, GR:$src2),
   "cmp.eq $dst1, dst2 = $src1, $src2">, isA;
 
-def ADDIMM14 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s14imm:$imm),
+def ADDIMM14 : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, s14imm:$imm),
   "adds $dst = $imm, $src1">, isA;
 
-def ADDIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s22imm:$imm),
+def ADDIMM22 : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, s22imm:$imm),
   "add $dst = $imm, $src1">, isA;
-def CADDIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s22imm:$imm, PR:$qp),
+def CADDIMM22 : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, s22imm:$imm, PR:$qp),
   "($qp) add $dst = $imm, $src1">, isA;
 
-def SUBIMM8 : AForm<0x03, 0x0b, (ops GR:$dst, s8imm:$imm, GR:$src2),
+def SUBIMM8 : AForm<0x03, 0x0b, (outs GR:$dst), (ins s8imm:$imm, GR:$src2),
   "sub $dst = $imm, $src2">, isA;
 
 let isStore = 1, noResults = 1 in {
-  def ST1 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value),
+  def ST1 : AForm<0x03, 0x0b, (outs), (ins GR:$dstPtr, GR:$value),
     "st1 [$dstPtr] = $value">, isM;
-  def ST2 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value),
+  def ST2 : AForm<0x03, 0x0b, (outs), (ins GR:$dstPtr, GR:$value),
     "st2 [$dstPtr] = $value">, isM;
-  def ST4 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value),
+  def ST4 : AForm<0x03, 0x0b, (outs), (ins GR:$dstPtr, GR:$value),
     "st4 [$dstPtr] = $value">, isM;
-  def ST8 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value),
+  def ST8 : AForm<0x03, 0x0b, (outs), (ins GR:$dstPtr, GR:$value),
     "st8 [$dstPtr] = $value">, isM;
-  def STF4 : AForm<0x03, 0x0b, (ops GR:$dstPtr, FP:$value),
+  def STF4 : AForm<0x03, 0x0b, (outs), (ins GR:$dstPtr, FP:$value),
     "stfs [$dstPtr] = $value">, isM;
-  def STF8 : AForm<0x03, 0x0b, (ops GR:$dstPtr, FP:$value),
+  def STF8 : AForm<0x03, 0x0b, (outs), (ins GR:$dstPtr, FP:$value),
     "stfd [$dstPtr] = $value">, isM;
-  def STF_SPILL : AForm<0x03, 0x0b, (ops GR:$dstPtr, FP:$value),
+  def STF_SPILL : AForm<0x03, 0x0b, (outs), (ins GR:$dstPtr, FP:$value),
     "stf.spill [$dstPtr] = $value">, isM;
 }
 
 let isLoad = 1 in {
-  def LD1 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$srcPtr),
+  def LD1 : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$srcPtr),
     "ld1 $dst = [$srcPtr]">, isM;
-  def LD2 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$srcPtr),
+  def LD2 : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$srcPtr),
     "ld2 $dst = [$srcPtr]">, isM;
-  def LD4 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$srcPtr),
+  def LD4 : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$srcPtr),
     "ld4 $dst = [$srcPtr]">, isM;
-  def LD8 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$srcPtr),
+  def LD8 : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$srcPtr),
     "ld8 $dst = [$srcPtr]">, isM;
-  def LDF4 : AForm<0x03, 0x0b, (ops FP:$dst, GR:$srcPtr),
+  def LDF4 : AForm<0x03, 0x0b, (outs FP:$dst), (ins GR:$srcPtr),
     "ldfs $dst = [$srcPtr]">, isM;
-  def LDF8 : AForm<0x03, 0x0b, (ops FP:$dst, GR:$srcPtr),
+  def LDF8 : AForm<0x03, 0x0b, (outs FP:$dst), (ins GR:$srcPtr),
     "ldfd $dst = [$srcPtr]">, isM;
-  def LDF_FILL : AForm<0x03, 0x0b, (ops FP:$dst, GR:$srcPtr),
+  def LDF_FILL : AForm<0x03, 0x0b, (outs FP:$dst), (ins GR:$srcPtr),
     "ldf.fill $dst = [$srcPtr]">, isM;
 }
 
-def POPCNT : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src),
+def POPCNT : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src),
   "popcnt $dst = $src",
   [(set GR:$dst, (ctpop GR:$src))]>, isI;
 
 // some FP stuff:  // TODO: single-precision stuff?
-def FADD : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2),
+def FADD : AForm_DAG<0x03, 0x0b, (outs FP:$dst), (ins FP:$src1, FP:$src2),
   "fadd $dst = $src1, $src2",
   [(set FP:$dst, (fadd FP:$src1, FP:$src2))]>, isF;
-def FADDS: AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2),
+def FADDS: AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src1, FP:$src2),
   "fadd.s $dst = $src1, $src2">, isF;
-def FSUB : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2),
+def FSUB : AForm_DAG<0x03, 0x0b, (outs FP:$dst), (ins FP:$src1, FP:$src2),
   "fsub $dst = $src1, $src2",
   [(set FP:$dst, (fsub FP:$src1, FP:$src2))]>, isF;
-def FMPY : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2),
+def FMPY : AForm_DAG<0x03, 0x0b, (outs FP:$dst), (ins FP:$src1, FP:$src2),
   "fmpy $dst = $src1, $src2",
   [(set FP:$dst, (fmul FP:$src1, FP:$src2))]>, isF;
-def FMA : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
+def FMA : AForm_DAG<0x03, 0x0b, (outs FP:$dst), (ins FP:$src1, FP:$src2, FP:$src3),
   "fma $dst = $src1, $src2, $src3",
   [(set FP:$dst, (fadd (fmul FP:$src1, FP:$src2), FP:$src3))]>, isF;
-def FMS : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
+def FMS : AForm_DAG<0x03, 0x0b, (outs FP:$dst), (ins FP:$src1, FP:$src2, FP:$src3),
   "fms $dst = $src1, $src2, $src3",
   [(set FP:$dst, (fsub (fmul FP:$src1, FP:$src2), FP:$src3))]>, isF;
-def FNMA : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
+def FNMA : AForm_DAG<0x03, 0x0b, (outs FP:$dst), (ins FP:$src1, FP:$src2, FP:$src3),
   "fnma $dst = $src1, $src2, $src3",
   [(set FP:$dst, (fneg (fadd (fmul FP:$src1, FP:$src2), FP:$src3)))]>, isF;
-def FABS : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src),
+def FABS : AForm_DAG<0x03, 0x0b, (outs FP:$dst), (ins FP:$src),
   "fabs $dst = $src",
   [(set FP:$dst, (fabs FP:$src))]>, isF;
-def FNEG : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src),
+def FNEG : AForm_DAG<0x03, 0x0b, (outs FP:$dst), (ins FP:$src),
   "fneg $dst = $src",
   [(set FP:$dst, (fneg FP:$src))]>, isF;
-def FNEGABS : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src),
+def FNEGABS : AForm_DAG<0x03, 0x0b, (outs FP:$dst), (ins FP:$src),
   "fnegabs $dst = $src",
   [(set FP:$dst, (fneg (fabs FP:$src)))]>, isF;
 
 let isTwoAddress=1 in {
 def TCFMAS1 : AForm<0x03, 0x0b,
-  (ops FP:$dst, FP:$bogussrc, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
+  (outs FP:$dst), (ins FP:$bogussrc, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
     "($qp) fma.s1 $dst = $src1, $src2, $src3">, isF;
 def TCFMADS0 : AForm<0x03, 0x0b,
-  (ops FP:$dst, FP:$bogussrc, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
+  (outs FP:$dst), (ins FP:$bogussrc, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
     "($qp) fma.d.s0 $dst = $src1, $src2, $src3">, isF;
 }
 
 def CFMAS1 : AForm<0x03, 0x0b,
-  (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
+  (outs FP:$dst), (ins FP:$src1, FP:$src2, FP:$src3, PR:$qp),
     "($qp) fma.s1 $dst = $src1, $src2, $src3">, isF;
 def CFNMAS1 : AForm<0x03, 0x0b,
-  (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
+  (outs FP:$dst), (ins FP:$src1, FP:$src2, FP:$src3, PR:$qp),
     "($qp) fnma.s1 $dst = $src1, $src2, $src3">, isF;
 
 def CFMADS1 : AForm<0x03, 0x0b,
-  (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
+  (outs FP:$dst), (ins FP:$src1, FP:$src2, FP:$src3, PR:$qp),
     "($qp) fma.d.s1 $dst = $src1, $src2, $src3">, isF;
 def CFMADS0 : AForm<0x03, 0x0b,
-  (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
+  (outs FP:$dst), (ins FP:$src1, FP:$src2, FP:$src3, PR:$qp),
     "($qp) fma.d.s0 $dst = $src1, $src2, $src3">, isF;
 def CFNMADS1 : AForm<0x03, 0x0b,
-  (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
+  (outs FP:$dst), (ins FP:$src1, FP:$src2, FP:$src3, PR:$qp),
     "($qp) fnma.d.s1 $dst = $src1, $src2, $src3">, isF;
 
-def FRCPAS0 : AForm<0x03, 0x0b, (ops FP:$dstFR, PR:$dstPR, FP:$src1, FP:$src2),
+def FRCPAS0 : AForm<0x03, 0x0b, (outs FP:$dstFR, PR:$dstPR), (ins FP:$src1, FP:$src2),
   "frcpa.s0 $dstFR, $dstPR = $src1, $src2">, isF;
-def FRCPAS1 : AForm<0x03, 0x0b, (ops FP:$dstFR, PR:$dstPR, FP:$src1, FP:$src2),
+def FRCPAS1 : AForm<0x03, 0x0b, (outs FP:$dstFR, PR:$dstPR), (ins FP:$src1, FP:$src2),
   "frcpa.s1 $dstFR, $dstPR = $src1, $src2">, isF;
 
-def XMAL : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
+def XMAL : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src1, FP:$src2, FP:$src3),
   "xma.l $dst = $src1, $src2, $src3">, isF;
 
-def FCVTXF : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
+def FCVTXF : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src),
   "fcvt.xf $dst = $src">, isF;
-def FCVTXUF : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
+def FCVTXUF : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src),
   "fcvt.xuf $dst = $src">, isF;
-def FCVTXUFS1 : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
+def FCVTXUFS1 : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src),
   "fcvt.xuf.s1 $dst = $src">, isF;
-def FCVTFX : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
+def FCVTFX : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src),
   "fcvt.fx $dst = $src">, isF;
-def FCVTFXU : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
+def FCVTFXU : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src),
   "fcvt.fxu $dst = $src">, isF;
 
-def FCVTFXTRUNC : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
+def FCVTFXTRUNC : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src),
   "fcvt.fx.trunc $dst = $src">, isF;
-def FCVTFXUTRUNC : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
+def FCVTFXUTRUNC : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src),
   "fcvt.fxu.trunc $dst = $src">, isF;
 
-def FCVTFXTRUNCS1 : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
+def FCVTFXTRUNCS1 : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src),
   "fcvt.fx.trunc.s1 $dst = $src">, isF;
-def FCVTFXUTRUNCS1 : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
+def FCVTFXUTRUNCS1 : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src),
   "fcvt.fxu.trunc.s1 $dst = $src">, isF;
 
-def FNORMD : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
+def FNORMD : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src),
   "fnorm.d $dst = $src">, isF;
 
-def GETFD : AForm<0x03, 0x0b, (ops GR:$dst, FP:$src),
+def GETFD : AForm<0x03, 0x0b, (outs GR:$dst), (ins FP:$src),
   "getf.d $dst = $src">, isM;
-def SETFD : AForm<0x03, 0x0b, (ops FP:$dst, GR:$src),
+def SETFD : AForm<0x03, 0x0b, (outs FP:$dst), (ins GR:$src),
   "setf.d $dst = $src">, isM;
 
-def GETFSIG : AForm<0x03, 0x0b, (ops GR:$dst, FP:$src),
+def GETFSIG : AForm<0x03, 0x0b, (outs GR:$dst), (ins FP:$src),
   "getf.sig $dst = $src">, isM;
-def SETFSIG : AForm<0x03, 0x0b, (ops FP:$dst, GR:$src),
+def SETFSIG : AForm<0x03, 0x0b, (outs FP:$dst), (ins GR:$src),
   "setf.sig $dst = $src">, isM;
 
 // these four FP<->int conversion patterns need checking/cleaning
@@ -688,11 +688,11 @@ def FP_TO_UINT : Pat<(i64 (fp_to_uint FP:$src)),
 
 
 let isTerminator = 1, isBranch = 1, noResults = 1 in {
-  def BRL_NOTCALL : RawForm<0x03, 0xb0, (ops i64imm:$dst),
+  def BRL_NOTCALL : RawForm<0x03, 0xb0, (outs), (ins i64imm:$dst),
     "(p0) brl.cond.sptk $dst">, isB;
-  def BRLCOND_NOTCALL : RawForm<0x03, 0xb0, (ops PR:$qp, i64imm:$dst),
+  def BRLCOND_NOTCALL : RawForm<0x03, 0xb0, (outs), (ins PR:$qp, i64imm:$dst),
     "($qp) brl.cond.sptk $dst">, isB;
-  def BRCOND_NOTCALL : RawForm<0x03, 0xb0, (ops PR:$qp, GR:$dst),
+  def BRCOND_NOTCALL : RawForm<0x03, 0xb0, (outs), (ins PR:$qp, GR:$dst),
     "($qp) br.cond.sptk $dst">, isB;
 }
 
@@ -713,32 +713,32 @@ let isCall = 1, noResults = 1, /* isTerminator = 1, isBranch = 1, */
   F120,F121,F122,F123,F124,F125,F126,F127,
   out0,out1,out2,out3,out4,out5,out6,out7] in {
 // old pattern call
-  def BRCALL: RawForm<0x03, 0xb0, (ops calltarget:$dst),
+  def BRCALL: RawForm<0x03, 0xb0, (outs), (ins calltarget:$dst),
   "br.call.sptk rp = $dst">, isB;   // FIXME: teach llvm about branch regs?
 // new daggy stuff!  
 
 // calls a globaladdress
-  def BRCALL_IPREL_GA : RawForm<0x03, 0xb0, (ops calltarget:$dst),
+  def BRCALL_IPREL_GA : RawForm<0x03, 0xb0, (outs), (ins calltarget:$dst),
   "br.call.sptk rp = $dst">, isB;       // FIXME: teach llvm about branch regs?
 // calls an externalsymbol
-  def BRCALL_IPREL_ES : RawForm<0x03, 0xb0, (ops calltarget:$dst),
+  def BRCALL_IPREL_ES : RawForm<0x03, 0xb0, (outs), (ins calltarget:$dst),
   "br.call.sptk rp = $dst">, isB;       // FIXME: teach llvm about branch regs?
 // calls through a function descriptor
-  def BRCALL_INDIRECT : RawForm<0x03, 0xb0, (ops GR:$branchreg),
+  def BRCALL_INDIRECT : RawForm<0x03, 0xb0, (outs), (ins GR:$branchreg),
   "br.call.sptk rp = $branchreg">, isB; // FIXME: teach llvm about branch regs?
-  def BRLCOND_CALL : RawForm<0x03, 0xb0, (ops PR:$qp, i64imm:$dst),
+  def BRLCOND_CALL : RawForm<0x03, 0xb0, (outs), (ins PR:$qp, i64imm:$dst),
     "($qp) brl.cond.call.sptk $dst">, isB;
-  def BRCOND_CALL : RawForm<0x03, 0xb0, (ops PR:$qp, GR:$dst),
+  def BRCOND_CALL : RawForm<0x03, 0xb0, (outs), (ins PR:$qp, GR:$dst),
     "($qp) br.cond.call.sptk $dst">, isB;
 }
 
 // Return branch:
 let isTerminator = 1, isReturn = 1, noResults = 1 in
-  def RET : AForm_DAG<0x03, 0x0b, (ops),
+  def RET : AForm_DAG<0x03, 0x0b, (outs), (ins),
             "br.ret.sptk.many rp",
             [(retflag)]>, isB; // return
 def : Pat<(ret), (RET)>;
 
 // the evil stop bit of despair
-def STOP : PseudoInstIA64<(ops variable_ops), ";;">;
+def STOP : PseudoInstIA64<(outs), (ins variable_ops), ";;">;