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| author | Duraid Madina <duraid@octopus.com.au> | 2006-01-20 16:10:05 +0000 |
|---|---|---|
| committer | Duraid Madina <duraid@octopus.com.au> | 2006-01-20 16:10:05 +0000 |
| commit | ecc1a1bb1e2027c9ebff67323dade67ec18b3ac6 (patch) | |
| tree | 97a1004ffd437aadcb707d7127d94c9cdec69fe8 /lib/Target/IA64 | |
| parent | eca86da38c5a779e06fddb903e9fa1ae262712d1 (diff) | |
| download | external_llvm-ecc1a1bb1e2027c9ebff67323dade67ec18b3ac6.zip external_llvm-ecc1a1bb1e2027c9ebff67323dade67ec18b3ac6.tar.gz external_llvm-ecc1a1bb1e2027c9ebff67323dade67ec18b3ac6.tar.bz2 | |
fix sext breakage: now we correctly deal with functions that return
int vs uint
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25478 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/IA64')
| -rw-r--r-- | lib/Target/IA64/IA64ISelDAGToDAG.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/IA64/IA64ISelLowering.cpp | 4 |
2 files changed, 5 insertions, 1 deletions
diff --git a/lib/Target/IA64/IA64ISelDAGToDAG.cpp b/lib/Target/IA64/IA64ISelDAGToDAG.cpp index 18637c2..5c5802e 100644 --- a/lib/Target/IA64/IA64ISelDAGToDAG.cpp +++ b/lib/Target/IA64/IA64ISelDAGToDAG.cpp @@ -494,7 +494,7 @@ SDOperand IA64DAGToDAGISel::Select(SDOperand Op) { */ case ISD::LOAD: - case ISD::EXTLOAD: + case ISD::EXTLOAD: // FIXME: load -1, not 1, for bools? case ISD::ZEXTLOAD: { SDOperand Chain = Select(N->getOperand(0)); SDOperand Address = Select(N->getOperand(1)); diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp index c4a4cdf..7e46fdf 100644 --- a/lib/Target/IA64/IA64ISelLowering.cpp +++ b/lib/Target/IA64/IA64ISelLowering.cpp @@ -475,6 +475,8 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain, switch (RetTyVT) { default: assert(0 && "Unknown value type to return!"); case MVT::i1: { // bools are just like other integers (returned in r8) + // we *could* fall through to the truncate below, but this saves a + // few redundant predicate ops SDOperand boolInR8 = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag); InFlag = boolInR8.getValue(2); Chain = boolInR8.getValue(1); @@ -492,8 +494,10 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain, Chain = RetVal.getValue(1); // keep track of whether it is sign or zero extended (todo: bools?) +/* XXX RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext, MVT::i64, RetVal, DAG.getValueType(RetTyVT)); +*/ RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); break; case MVT::i64: |