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| author | Wesley Peck <peckw@wesleypeck.com> | 2010-10-21 19:48:38 +0000 |
|---|---|---|
| committer | Wesley Peck <peckw@wesleypeck.com> | 2010-10-21 19:48:38 +0000 |
| commit | 4da992aebada7445ef68a7b6b94676dd26e9d537 (patch) | |
| tree | 535f86b7d5284f8c0be9ee7364e1acfd0ac9a971 /lib/Target/MBlaze/TODO | |
| parent | bc078c81e66cbd0263fb75f533a63ac7dd1f137d (diff) | |
| download | external_llvm-4da992aebada7445ef68a7b6b94676dd26e9d537.zip external_llvm-4da992aebada7445ef68a7b6b94676dd26e9d537.tar.gz external_llvm-4da992aebada7445ef68a7b6b94676dd26e9d537.tar.bz2 | |
Adding initial AsmParser implementation for the MBlaze backend. It is
mostly based on the ARM AsmParser at this time and is not particularly
functional.
Changed the MBlaze data layout from:
"E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32"
to:
"E-p:32:32:32-i8:8:8-i16:16:16"
because the MicroBlaze doesn't have i64, f64, v64, or v128 data types.
Cleaned up the MBlaze source code:
1. The floating point register class has been removed. The
MicroBlaze does not have floating point registers. Floating
point values are simply stored in integer registers.
2. Renaming the CPURegs register class to GPR to reflect the
standard naming.
3. Removing a lot of stale code from AsmPrinter after
the conversion to InstPrinter.
4. Simplified sign extended loads by marking them as
expanded in ISelLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117054 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/MBlaze/TODO')
| -rw-r--r-- | lib/Target/MBlaze/TODO | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/lib/Target/MBlaze/TODO b/lib/Target/MBlaze/TODO index 737f111..67434e9 100644 --- a/lib/Target/MBlaze/TODO +++ b/lib/Target/MBlaze/TODO @@ -16,6 +16,10 @@ branch += 32768 bytes (~8192 instructions). We should allow conditional branches to use 4-byte relocations but I'm not sure how to do that right now. + - Relocation records for indirect calls are not being generated + correctly. These should emit and IMM 0 directly before the ORI + instruction that loads the register (just like when a BRLID + instruction is used instead of an ORI). * Code generation seems to work relatively well now but the following needs to be examined more closely: @@ -24,3 +28,5 @@ - The delay slot filler is ad hoc but seems to work. Load and store instructions were prevented from being moved to delay slots but I'm not sure that is necessary. + - The processor itineraries are copied from a different backend + and need to be updated to model the MicroBlaze correctly. |