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authorJakob Stoklund Olesen <stoklund@2pi.dk>2010-05-26 01:21:14 +0000
committerJakob Stoklund Olesen <stoklund@2pi.dk>2010-05-26 01:21:14 +0000
commit6befc4388b163a196007644913cfe921d7b5ac26 (patch)
tree96d997b82dbd5e9fa80e40dd406b0e55db187b2d /lib/Target/MSP430
parentfb562b309c80b8f531ac88325f0774eac3456a89 (diff)
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external_llvm-6befc4388b163a196007644913cfe921d7b5ac26.tar.gz
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Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."
This reverts commit 104654. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104660 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/MSP430')
-rw-r--r--lib/Target/MSP430/MSP430RegisterInfo.td11
1 files changed, 7 insertions, 4 deletions
diff --git a/lib/Target/MSP430/MSP430RegisterInfo.td b/lib/Target/MSP430/MSP430RegisterInfo.td
index f8aec66..f488f00 100644
--- a/lib/Target/MSP430/MSP430RegisterInfo.td
+++ b/lib/Target/MSP430/MSP430RegisterInfo.td
@@ -43,9 +43,6 @@ def R13B : MSP430Reg<13, "r13">;
def R14B : MSP430Reg<14, "r14">;
def R15B : MSP430Reg<15, "r15">;
-def subreg_8bit : SubRegIndex { let Namespace = "MSP430"; }
-
-let SubRegIndices = [subreg_8bit] in {
def PCW : MSP430RegWithSubregs<0, "r0", [PCB]>;
def SPW : MSP430RegWithSubregs<1, "r1", [SPB]>;
def SRW : MSP430RegWithSubregs<2, "r2", [SRB]>;
@@ -62,7 +59,13 @@ def R12W : MSP430RegWithSubregs<12, "r12", [R12B]>;
def R13W : MSP430RegWithSubregs<13, "r13", [R13B]>;
def R14W : MSP430RegWithSubregs<14, "r14", [R14B]>;
def R15W : MSP430RegWithSubregs<15, "r15", [R15B]>;
-}
+
+def subreg_8bit : SubRegIndex { let Namespace = "MSP430"; }
+
+def : SubRegSet<subreg_8bit, [PCW, SPW, SRW, CGW, FPW, R5W, R6W, R7W,
+ R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
+ [PCB, SPB, SRB, CGB, FPB, R5B, R6B, R7B,
+ R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
def GR8 : RegisterClass<"MSP430", [i8], 8,
// Volatile registers