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authorAkira Hatanaka <ahatanaka@mips.com>2013-08-06 22:20:40 +0000
committerAkira Hatanaka <ahatanaka@mips.com>2013-08-06 22:20:40 +0000
commita1fe9ef62e18dcb30cdee62a2fad82d05791d359 (patch)
tree20fa85aa5d7556de021742e5ddf54030f4eb8ece /lib/Target/Mips/AsmParser/MipsAsmParser.cpp
parent0880939a590abab124c8520aaa4ac5a46f1937c6 (diff)
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[mips] Replace usages of register classes with register operands. Also, remove
unnecessary jalr InstAliases in Mips64InstrInfo.td and add the code to print jalr InstAliases in MipsInstPrinter::printAlias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187821 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/AsmParser/MipsAsmParser.cpp')
-rw-r--r--lib/Target/Mips/AsmParser/MipsAsmParser.cpp46
1 files changed, 44 insertions, 2 deletions
diff --git a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 7e7b39b..4b419ad 100644
--- a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -114,6 +114,9 @@ class MipsAsmParser : public MCTargetAsmParser {
MipsAsmParser::OperandMatchResultTy
parseFCCRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
+ MipsAsmParser::OperandMatchResultTy
+ parseACRegsDSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
+
bool searchSymbolAlias(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
unsigned RegKind);
@@ -223,7 +226,8 @@ public:
Kind_FGR64Regs,
Kind_AFGR64Regs,
Kind_CCRRegs,
- Kind_FCCRegs
+ Kind_FCCRegs,
+ Kind_ACRegsDSP
};
private:
@@ -410,6 +414,10 @@ public:
return (Kind == k_Register) && Reg.Kind == Kind_FCCRegs;
}
+ bool isACRegsDSPAsm() const {
+ return Kind == k_Register && Reg.Kind == Kind_ACRegsDSP;
+ }
+
/// getStartLoc - Get the location of the first token of this operand.
SMLoc getStartLoc() const {
return StartLoc;
@@ -1272,7 +1280,8 @@ MipsAsmParser::parseRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
return MatchOperand_NoMatch;
Parser.Lex(); // Eat $
- if (!tryParseRegisterOperand(Operands, isMips64())) {
+ if (!tryParseRegisterOperand(Operands,
+ RegKind == MipsOperand::Kind_CPU64Regs)) {
// Set the proper register kind.
MipsOperand* op = static_cast<MipsOperand*>(Operands.back());
op->setRegKind(Kind);
@@ -1367,6 +1376,39 @@ MipsAsmParser::parseFCCRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
return MatchOperand_Success;
}
+MipsAsmParser::OperandMatchResultTy
+MipsAsmParser::parseACRegsDSP(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
+ // If the first token is not '$' we have an error.
+ if (Parser.getTok().isNot(AsmToken::Dollar))
+ return MatchOperand_NoMatch;
+
+ SMLoc S = Parser.getTok().getLoc();
+ Parser.Lex(); // Eat the '$'
+
+ const AsmToken &Tok = Parser.getTok(); // Get next token.
+
+ if (Tok.isNot(AsmToken::Identifier))
+ return MatchOperand_NoMatch;
+
+ if (!Tok.getIdentifier().startswith("acc"))
+ return MatchOperand_NoMatch;
+
+ StringRef NumString = Tok.getIdentifier().substr(3);
+
+ unsigned IntVal;
+ if (NumString.getAsInteger(10, IntVal))
+ return MatchOperand_NoMatch;
+
+ unsigned Reg = matchRegisterByNumber(IntVal, Mips::ACRegsDSPRegClassID);
+
+ MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
+ Op->setRegKind(MipsOperand::Kind_ACRegsDSP);
+ Operands.push_back(Op);
+
+ Parser.Lex(); // Eat the register number.
+ return MatchOperand_Success;
+}
+
bool MipsAsmParser::searchSymbolAlias(
SmallVectorImpl<MCParsedAsmOperand*> &Operands, unsigned RegKind) {