diff options
author | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2008-07-05 19:05:21 +0000 |
---|---|---|
committer | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2008-07-05 19:05:21 +0000 |
commit | 225ca9cdd70de3d12641b0aba7daf6cb568a7ebd (patch) | |
tree | 4e9448b1e96f4e7792d2dcb85781c53ddef8dd39 /lib/Target/Mips/Mips.td | |
parent | 126d90770bdb17e6925b2fe26de99aa079b7b9b3 (diff) | |
download | external_llvm-225ca9cdd70de3d12641b0aba7daf6cb568a7ebd.zip external_llvm-225ca9cdd70de3d12641b0aba7daf6cb568a7ebd.tar.gz external_llvm-225ca9cdd70de3d12641b0aba7daf6cb568a7ebd.tar.bz2 |
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/Mips.td')
-rw-r--r-- | lib/Target/Mips/Mips.td | 39 |
1 files changed, 30 insertions, 9 deletions
diff --git a/lib/Target/Mips/Mips.td b/lib/Target/Mips/Mips.td index 50a5f65..1199cc4 100644 --- a/lib/Target/Mips/Mips.td +++ b/lib/Target/Mips/Mips.td @@ -16,7 +16,7 @@ include "../Target.td" //===----------------------------------------------------------------------===// -// Descriptions +// Register File, Calling Conv, Instruction Descriptions //===----------------------------------------------------------------------===// include "MipsRegisterInfo.td" @@ -30,22 +30,43 @@ def MipsInstrInfo : InstrInfo { } //===----------------------------------------------------------------------===// -// CPU Directives // +// Mips Subtarget features // //===----------------------------------------------------------------------===// -// Not currently supported, but work as SubtargetFeature placeholder. -def FeatureMipsIII : SubtargetFeature<"mips3", "IsMipsIII", "true", - "MipsIII ISA Support">; +def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true", + "General Purpose Registers are 64-bit wide.">; +def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true", + "Support 64-bit FP registers.">; +def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat", + "true", "Only supports single precision float">; +def FeatureAllegrexVFPU : SubtargetFeature<"allegrex-vfpu", "HasAllegrexVFPU", + "true", "Enable Allegrex VFPU instructions.">; +def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2", + "Mips2 ISA Support">; +def FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32", + "Enable o32 ABI">; +def FeatureEABI : SubtargetFeature<"eabi", "MipsABI", "EABI", + "Enable eabi ABI">; //===----------------------------------------------------------------------===// // Mips processors supported. //===----------------------------------------------------------------------===// -def : Processor<"mips1", MipsGenericItineraries, []>; -def : Processor<"r2000", MipsGenericItineraries, []>; -def : Processor<"r3000", MipsGenericItineraries, []>; +class Proc<string Name, list<SubtargetFeature> Features> + : Processor<Name, MipsGenericItineraries, Features>; + +def : Proc<"mips1", []>; +def : Proc<"r2000", []>; +def : Proc<"r3000", []>; + +def : Proc<"mips2", [FeatureMips2]>; +def : Proc<"r6000", [FeatureMips2]>; + +// Allegrex is a 32bit subset of r4000, both for interger and fp registers, +// but much more similar to Mips2 than Mips3. +def : Proc<"allegrex", [FeatureMips2, FeatureSingleFloat, FeatureAllegrexVFPU, + FeatureEABI]>; def Mips : Target { let InstructionSet = MipsInstrInfo; } - |