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author | Akira Hatanaka <ahatanaka@mips.com> | 2012-08-17 20:16:42 +0000 |
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committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-08-17 20:16:42 +0000 |
commit | 72e9b6aeb48d9496bac9db8b02c88a618b464588 (patch) | |
tree | 4d9fc91cc8ee09c3e890cf494337717ec5ee7d56 /lib/Target/Mips/Mips.td | |
parent | 168843c0137ad67c24a3930244a9c5f60add320d (diff) | |
download | external_llvm-72e9b6aeb48d9496bac9db8b02c88a618b464588.zip external_llvm-72e9b6aeb48d9496bac9db8b02c88a618b464588.tar.gz external_llvm-72e9b6aeb48d9496bac9db8b02c88a618b464588.tar.bz2 |
Add stub methods for mips assembly matcher.
Patch by Vladimir Medic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162124 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/Mips.td')
-rw-r--r-- | lib/Target/Mips/Mips.td | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/lib/Target/Mips/Mips.td b/lib/Target/Mips/Mips.td index 90f7942..7cec531 100644 --- a/lib/Target/Mips/Mips.td +++ b/lib/Target/Mips/Mips.td @@ -95,9 +95,20 @@ def MipsAsmWriter : AsmWriter { bit isMCAsmWriter = 1; } +def MipsAsmParser : AsmParser { + let ShouldEmitMatchRegisterName = 0; +} + +def MipsAsmParserVariant : AsmParserVariant { + int Variant = 0; + + // Recognize hard coded registers. + string RegisterPrefix = "$"; +} + def Mips : Target { let InstructionSet = MipsInstrInfo; - + let AssemblyParsers = [MipsAsmParser]; let AssemblyWriters = [MipsAsmWriter]; + let AssemblyParserVariants = [MipsAsmParserVariant]; } - |