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| author | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2008-07-09 05:32:22 +0000 |
|---|---|---|
| committer | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2008-07-09 05:32:22 +0000 |
| commit | 7728f7e890fd326af6948c52092fc9ea4f38c986 (patch) | |
| tree | 81e5bcd86dd1ec3197496149894cbe309e5193d8 /lib/Target/Mips/Mips.td | |
| parent | d1f77bf9312e93c62e651a8cdc2cbee68a21f1c1 (diff) | |
| download | external_llvm-7728f7e890fd326af6948c52092fc9ea4f38c986.zip external_llvm-7728f7e890fd326af6948c52092fc9ea4f38c986.tar.gz external_llvm-7728f7e890fd326af6948c52092fc9ea4f38c986.tar.bz2 | |
Fixed features usage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53277 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/Mips.td')
| -rw-r--r-- | lib/Target/Mips/Mips.td | 22 |
1 files changed, 12 insertions, 10 deletions
diff --git a/lib/Target/Mips/Mips.td b/lib/Target/Mips/Mips.td index 1199cc4..bb83fc0 100644 --- a/lib/Target/Mips/Mips.td +++ b/lib/Target/Mips/Mips.td @@ -33,20 +33,22 @@ def MipsInstrInfo : InstrInfo { // Mips Subtarget features // //===----------------------------------------------------------------------===// -def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true", +def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true", "General Purpose Registers are 64-bit wide.">; -def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true", +def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true", "Support 64-bit FP registers.">; -def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat", +def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat", "true", "Only supports single precision float">; -def FeatureAllegrexVFPU : SubtargetFeature<"allegrex-vfpu", "HasAllegrexVFPU", - "true", "Enable Allegrex VFPU instructions.">; -def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2", +def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2", "Mips2 ISA Support">; -def FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32", +def FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32", "Enable o32 ABI">; -def FeatureEABI : SubtargetFeature<"eabi", "MipsABI", "EABI", +def FeatureEABI : SubtargetFeature<"eabi", "MipsABI", "EABI", "Enable eabi ABI">; +def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU", + "true", "Enable vector FPU instructions.">; +def FeatureSEInReg : SubtargetFeature<"seinreg", "HasSEInReg", "true", + "Enable 'signext in register' instructions.">; //===----------------------------------------------------------------------===// // Mips processors supported. @@ -64,8 +66,8 @@ def : Proc<"r6000", [FeatureMips2]>; // Allegrex is a 32bit subset of r4000, both for interger and fp registers, // but much more similar to Mips2 than Mips3. -def : Proc<"allegrex", [FeatureMips2, FeatureSingleFloat, FeatureAllegrexVFPU, - FeatureEABI]>; +def : Proc<"allegrex", [FeatureMips2, FeatureSingleFloat, FeatureEABI, + FeatureSEInReg, FeatureVFPU]>; def Mips : Target { let InstructionSet = MipsInstrInfo; |