diff options
author | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2008-07-30 17:01:06 +0000 |
---|---|---|
committer | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2008-07-30 17:01:06 +0000 |
commit | d3a680dda5b45bc20b0257358b83088e805373e9 (patch) | |
tree | 9fc92419e045c3320e29805820a571f5809b30d5 /lib/Target/Mips/Mips.td | |
parent | f7d66f73459f88ec3323bd9e8caa2b75cef49d9f (diff) | |
download | external_llvm-d3a680dda5b45bc20b0257358b83088e805373e9.zip external_llvm-d3a680dda5b45bc20b0257358b83088e805373e9.tar.gz external_llvm-d3a680dda5b45bc20b0257358b83088e805373e9.tar.bz2 |
Added new features to represent specific instructions groups
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54213 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/Mips.td')
-rw-r--r-- | lib/Target/Mips/Mips.td | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/lib/Target/Mips/Mips.td b/lib/Target/Mips/Mips.td index bb83fc0..79c1890 100644 --- a/lib/Target/Mips/Mips.td +++ b/lib/Target/Mips/Mips.td @@ -49,6 +49,16 @@ def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU", "true", "Enable vector FPU instructions.">; def FeatureSEInReg : SubtargetFeature<"seinreg", "HasSEInReg", "true", "Enable 'signext in register' instructions.">; +def FeatureCondMov : SubtargetFeature<"condmov", "HasCondMov", "true", + "Enable 'conditional move' instructions.">; +def FeatureMulDivAdd : SubtargetFeature<"muldivadd", "HasMulDivAdd", "true", + "Enable 'multiply add/sub' instructions.">; +def FeatureMinMax : SubtargetFeature<"minmax", "HasMinMax", "true", + "Enable 'min/max' instructions.">; +def FeatureSwap : SubtargetFeature<"swap", "HasSwap", "true", + "Enable 'byte/half swap' instructions.">; +def FeatureBitCount : SubtargetFeature<"bitcount", "HasBitCount", "true", + "Enable 'count leading bits' instructions.">; //===----------------------------------------------------------------------===// // Mips processors supported. @@ -65,9 +75,11 @@ def : Proc<"mips2", [FeatureMips2]>; def : Proc<"r6000", [FeatureMips2]>; // Allegrex is a 32bit subset of r4000, both for interger and fp registers, -// but much more similar to Mips2 than Mips3. +// but much more similar to Mips2 than Mips3. It also contains some of +// Mips32/Mips32r2 instructions and a custom vector fpu processor. def : Proc<"allegrex", [FeatureMips2, FeatureSingleFloat, FeatureEABI, - FeatureSEInReg, FeatureVFPU]>; + FeatureVFPU, FeatureSEInReg, FeatureCondMov, FeatureMulDivAdd, + FeatureMinMax, FeatureSwap, FeatureBitCount]>; def Mips : Target { let InstructionSet = MipsInstrInfo; |