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| author | Akira Hatanaka <ahatanaka@mips.com> | 2012-07-17 22:55:34 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-07-17 22:55:34 +0000 |
| commit | e882accb7a0e348bc86cca969e94e4c61581a4c8 (patch) | |
| tree | bddf8aa4008735b2c0bb3e3dd476d8feb4457b50 /lib/Target/Mips/Mips16InstrInfo.td | |
| parent | afb24cecff868e76ce37cfbe8fe2463fd6ae6993 (diff) | |
| download | external_llvm-e882accb7a0e348bc86cca969e94e4c61581a4c8.zip external_llvm-e882accb7a0e348bc86cca969e94e4c61581a4c8.tar.gz external_llvm-e882accb7a0e348bc86cca969e94e4c61581a4c8.tar.bz2 | |
Clean up Mips16InstrFormats.td and Mips16InstrInfo.td.
Patch by Reed Kotler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160403 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/Mips16InstrInfo.td')
| -rw-r--r-- | lib/Target/Mips/Mips16InstrInfo.td | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/lib/Target/Mips/Mips16InstrInfo.td b/lib/Target/Mips/Mips16InstrInfo.td index 4fd8dd4..71801ca 100644 --- a/lib/Target/Mips/Mips16InstrInfo.td +++ b/lib/Target/Mips/Mips16InstrInfo.td @@ -26,9 +26,9 @@ def LI16E : FEXT_RI16<0b01101, (outs CPU16Regs:$rx), [(set CPU16Regs:$rx, immZExt16:$amt )],IILoad>; let isReturn=1, isTerminator=1, hasDelaySlot=1, isCodeGenOnly=1, - isBarrier=1, hasCtrlDep=1, rx=0, nd=0, l=0, ra=0 in -def RET16 : FRR16_JALRC<(outs), (ins CPURAReg:$target), "jr\t$target", [], - IIBranch>; + isBarrier=1, hasCtrlDep=1, rx=0 in +def RET16 : FRR16_JALRC + <0,0,0, (outs), (ins CPURAReg:$target), "jr\t$target", [], IIBranch>; // As stack alignment is always done with addiu, we need a 16-bit immediate let Defs = [SP], Uses = [SP] in { @@ -42,10 +42,11 @@ def ADJCALLSTACKUP16 : MipsPseudo16<(outs), (ins uimm16:$amt1, uimm16:$amt2), // Jump and Link (Call) -let isCall=1, hasDelaySlot=1, nd=0, l=0, ra=0 in +let isCall=1, hasDelaySlot=1 in def JumpLinkReg16: - FRR16_JALRC<(outs), (ins CPU16Regs:$rs), - "jalr \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>; + FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs), + "jalr \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>; + // Small immediates def : Mips16Pat<(i32 immZExt16:$in), (LI16E immZExt16:$in)>; |