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| author | Akira Hatanaka <ahatanaka@mips.com> | 2013-02-07 19:48:00 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-02-07 19:48:00 +0000 |
| commit | 0c66403efdf88ff4f247b6a9f45339bb3a893235 (patch) | |
| tree | 7cec1e1f88759a2601ab41f7a0636a673e5c7a58 /lib/Target/Mips/Mips64InstrInfo.td | |
| parent | 184f5c1545e06a99951f14d846a1d853ff19a2b8 (diff) | |
| download | external_llvm-0c66403efdf88ff4f247b6a9f45339bb3a893235.zip external_llvm-0c66403efdf88ff4f247b6a9f45339bb3a893235.tar.gz external_llvm-0c66403efdf88ff4f247b6a9f45339bb3a893235.tar.bz2 | |
[mips] Add definition of JALR instruction which has two register operands. Change the
original JALR instruction with one register operand to be a pseudo-instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174657 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/Mips64InstrInfo.td')
| -rw-r--r-- | lib/Target/Mips/Mips64InstrInfo.td | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index db92c64..494ba87 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -170,6 +170,7 @@ def BLTZ64 : CBranchZero<"bltz", setlt, CPU64Regs>, BGEZ_FM<1, 0>; } let DecoderNamespace = "Mips64" in def JALR64 : JumpLinkReg<"jalr", CPU64Regs>, JALR_FM; +def JALR64Pseudo : JumpLinkRegPseudo<CPU64Regs, JALR64, RA_64>; def TAILCALL64_R : JumpFR<CPU64Regs, MipsTailCall>, MTLO_FM<8>, IsTailCall; let DecoderNamespace = "Mips64" in { @@ -329,6 +330,8 @@ def : InstAlias<"not $rt, $rs", (NOR64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rs, ZERO_64), 1>, Requires<[HasMips64]>; def : InstAlias<"j $rs", (JR64 CPU64Regs:$rs), 0>, Requires<[HasMips64]>; +def : InstAlias<"jalr $rs", (JALR64 RA_64, CPU64Regs:$rs)>, + Requires<[HasMips64]>; def : InstAlias<"daddu $rs, $rt, $imm", (DADDiu CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm), 1>; |