diff options
| author | Akira Hatanaka <ahatanaka@mips.com> | 2012-12-21 22:58:55 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-12-21 22:58:55 +0000 |
| commit | 16164657d88c50be59a3fbff035ded786a98cf7f (patch) | |
| tree | 8bbb25d1729f011c0614dff4ebbc78bc8377f9a0 /lib/Target/Mips/Mips64InstrInfo.td | |
| parent | 5f5770baae0bd586410c11e0be1f634415d41186 (diff) | |
| download | external_llvm-16164657d88c50be59a3fbff035ded786a98cf7f.zip external_llvm-16164657d88c50be59a3fbff035ded786a98cf7f.tar.gz external_llvm-16164657d88c50be59a3fbff035ded786a98cf7f.tar.bz2 | |
[mips] Refactor load/store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170948 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/Mips64InstrInfo.td')
| -rw-r--r-- | lib/Target/Mips/Mips64InstrInfo.td | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index c37f618..17455b7 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -128,17 +128,17 @@ let Predicates = [HasMips64r2, HasStdEnc], let DecoderNamespace = "Mips64" in { /// Load and Store Instructions /// aligned -defm LB64 : LoadM64<0x20, "lb", sextloadi8>; -defm LBu64 : LoadM64<0x24, "lbu", zextloadi8>; -defm LH64 : LoadM64<0x21, "lh", sextloadi16>; -defm LHu64 : LoadM64<0x25, "lhu", zextloadi16>; -defm LW64 : LoadM64<0x23, "lw", sextloadi32>; -defm LWu64 : LoadM64<0x27, "lwu", zextloadi32>; -defm SB64 : StoreM64<0x28, "sb", truncstorei8>; -defm SH64 : StoreM64<0x29, "sh", truncstorei16>; -defm SW64 : StoreM64<0x2b, "sw", truncstorei32>; -defm LD : LoadM64<0x37, "ld", load>; -defm SD : StoreM64<0x3f, "sd", store>; +defm LB64 : LoadM<"lb", sextloadi8, CPU64Regs>, LW_FM<0x20>; +defm LBu64 : LoadM<"lbu", zextloadi8, CPU64Regs>, LW_FM<0x24>; +defm LH64 : LoadM<"lh", sextloadi16, CPU64Regs>, LW_FM<0x21>; +defm LHu64 : LoadM<"lhu", zextloadi16, CPU64Regs>, LW_FM<0x25>; +defm LW64 : LoadM<"lw", sextloadi32, CPU64Regs>, LW_FM<0x23>; +defm LWu64 : LoadM<"lwu", zextloadi32, CPU64Regs>, LW_FM<0x27>; +defm SB64 : StoreM<"sb", truncstorei8, CPU64Regs>, LW_FM<0x28>; +defm SH64 : StoreM<"sh", truncstorei16, CPU64Regs>, LW_FM<0x29>; +defm SW64 : StoreM<"sw", truncstorei32, CPU64Regs>, LW_FM<0x2b>; +defm LD : LoadM<"ld", load, CPU64Regs>, LW_FM<0x37>; +defm SD : StoreM<"sd", store, CPU64Regs>, LW_FM<0x3f>; /// load/store left/right let isCodeGenOnly = 1 in { |