diff options
author | Akira Hatanaka <ahatanaka@mips.com> | 2012-07-10 00:19:06 +0000 |
---|---|---|
committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-07-10 00:19:06 +0000 |
commit | 182ef6fcaacbf44e17a96ea6614cbb5e1af1c3c2 (patch) | |
tree | decad739be2bc54c93de22590effcc899df32658 /lib/Target/Mips/Mips64InstrInfo.td | |
parent | 655b5a48b956d91e8656d8d2ef062dd9c2bf8591 (diff) | |
download | external_llvm-182ef6fcaacbf44e17a96ea6614cbb5e1af1c3c2.zip external_llvm-182ef6fcaacbf44e17a96ea6614cbb5e1af1c3c2.tar.gz external_llvm-182ef6fcaacbf44e17a96ea6614cbb5e1af1c3c2.tar.bz2 |
Make register Mips::RA allocatable if not in mips16 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159971 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/Mips64InstrInfo.td')
-rw-r--r-- | lib/Target/Mips/Mips64InstrInfo.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index a5a3038..7a9d41b 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -168,7 +168,7 @@ def SCD_P8 : SCBase<0x3c, "scd", CPU64Regs, mem64>, } /// Jump and Branch Instructions -def JR64 : JumpFR<0x00, 0x08, "jr", CPU64Regs>; +def JR64 : IndirectBranch<CPU64Regs>; def BEQ64 : CBranch<0x04, "beq", seteq, CPU64Regs>; def BNE64 : CBranch<0x05, "bne", setne, CPU64Regs>; def BGEZ64 : CBranchZero<0x01, 1, "bgez", setge, CPU64Regs>; |