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| author | Akira Hatanaka <ahatanaka@mips.com> | 2012-12-20 04:20:09 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-12-20 04:20:09 +0000 |
| commit | 1e7739f6140da773b6e998525d7900fa82670f00 (patch) | |
| tree | 9f66500b4bbf2f9d480dc7c32b9442a0dc439eaa /lib/Target/Mips/Mips64InstrInfo.td | |
| parent | 77e85f367c4f69fb95a88419aba1eef2cbab6800 (diff) | |
| download | external_llvm-1e7739f6140da773b6e998525d7900fa82670f00.zip external_llvm-1e7739f6140da773b6e998525d7900fa82670f00.tar.gz external_llvm-1e7739f6140da773b6e998525d7900fa82670f00.tar.bz2 | |
[mips] Remove asm string parameter from pseudo instructions. Add InstrItinClass
parameter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170661 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/Mips64InstrInfo.td')
| -rw-r--r-- | lib/Target/Mips/Mips64InstrInfo.td | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index 9b4b07b..0a3a500 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -46,19 +46,19 @@ class Mult64<bits<6> func, string instr_asm, InstrItinClass itin>: class Div64<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>: Div<op, func, instr_asm, itin, CPU64Regs, [HI64, LO64]>; -multiclass Atomic2Ops64<PatFrag Op, string Opstr> { - def #NAME# : Atomic2Ops<Op, Opstr, CPU64Regs, CPURegs>, +multiclass Atomic2Ops64<PatFrag Op> { + def #NAME# : Atomic2Ops<Op, CPU64Regs, CPURegs>, Requires<[NotN64, HasStdEnc]>; - def _P8 : Atomic2Ops<Op, Opstr, CPU64Regs, CPU64Regs>, + def _P8 : Atomic2Ops<Op, CPU64Regs, CPU64Regs>, Requires<[IsN64, HasStdEnc]> { let isCodeGenOnly = 1; } } -multiclass AtomicCmpSwap64<PatFrag Op, string Width> { - def #NAME# : AtomicCmpSwap<Op, Width, CPU64Regs, CPURegs>, +multiclass AtomicCmpSwap64<PatFrag Op> { + def #NAME# : AtomicCmpSwap<Op, CPU64Regs, CPURegs>, Requires<[NotN64, HasStdEnc]>; - def _P8 : AtomicCmpSwap<Op, Width, CPU64Regs, CPU64Regs>, + def _P8 : AtomicCmpSwap<Op, CPU64Regs, CPU64Regs>, Requires<[IsN64, HasStdEnc]> { let isCodeGenOnly = 1; } @@ -66,14 +66,14 @@ multiclass AtomicCmpSwap64<PatFrag Op, string Width> { } let usesCustomInserter = 1, Predicates = [HasStdEnc], DecoderNamespace = "Mips64" in { - defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64<atomic_load_add_64, "load_add_64">; - defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64<atomic_load_sub_64, "load_sub_64">; - defm ATOMIC_LOAD_AND_I64 : Atomic2Ops64<atomic_load_and_64, "load_and_64">; - defm ATOMIC_LOAD_OR_I64 : Atomic2Ops64<atomic_load_or_64, "load_or_64">; - defm ATOMIC_LOAD_XOR_I64 : Atomic2Ops64<atomic_load_xor_64, "load_xor_64">; - defm ATOMIC_LOAD_NAND_I64 : Atomic2Ops64<atomic_load_nand_64, "load_nand_64">; - defm ATOMIC_SWAP_I64 : Atomic2Ops64<atomic_swap_64, "swap_64">; - defm ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap64<atomic_cmp_swap_64, "64">; + defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64<atomic_load_add_64>; + defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64<atomic_load_sub_64>; + defm ATOMIC_LOAD_AND_I64 : Atomic2Ops64<atomic_load_and_64>; + defm ATOMIC_LOAD_OR_I64 : Atomic2Ops64<atomic_load_or_64>; + defm ATOMIC_LOAD_XOR_I64 : Atomic2Ops64<atomic_load_xor_64>; + defm ATOMIC_LOAD_NAND_I64 : Atomic2Ops64<atomic_load_nand_64>; + defm ATOMIC_SWAP_I64 : Atomic2Ops64<atomic_swap_64>; + defm ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap64<atomic_cmp_swap_64>; } //===----------------------------------------------------------------------===// |