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| author | Akira Hatanaka <ahatanaka@mips.com> | 2012-12-20 03:52:08 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-12-20 03:52:08 +0000 |
| commit | 2427773f2f18a2dd630428d7df927a5cdf4280f1 (patch) | |
| tree | 729f54d39fee680acb03d9f55d68c49d39134410 /lib/Target/Mips/Mips64InstrInfo.td | |
| parent | cdc0c59d1ed5ac6c616b8899222d1e102ccd9f8d (diff) | |
| download | external_llvm-2427773f2f18a2dd630428d7df927a5cdf4280f1.zip external_llvm-2427773f2f18a2dd630428d7df927a5cdf4280f1.tar.gz external_llvm-2427773f2f18a2dd630428d7df927a5cdf4280f1.tar.bz2 | |
[mips] Change the order of template parameters. Move the default parameters to
the end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170651 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/Mips64InstrInfo.td')
| -rw-r--r-- | lib/Target/Mips/Mips64InstrInfo.td | 23 |
1 files changed, 11 insertions, 12 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index c57c349..9b548a7 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -81,29 +81,28 @@ let usesCustomInserter = 1, Predicates = [HasStdEnc], //===----------------------------------------------------------------------===// let DecoderNamespace = "Mips64" in { /// Arithmetic Instructions (ALU Immediate) -def DADDi : ArithLogicI<"daddi", simm16_64, immSExt16, CPU64Regs>, - ADDI_FM<0x18>; -def DADDiu : ArithLogicI<"daddiu", simm16_64, immSExt16, CPU64Regs, add>, +def DADDi : ArithLogicI<"daddi", simm16_64, CPU64Regs>, ADDI_FM<0x18>; +def DADDiu : ArithLogicI<"daddiu", simm16_64, CPU64Regs, immSExt16, add>, ADDI_FM<0x19>, IsAsCheapAsAMove; -def DANDi : ArithLogicI<"andi", uimm16_64, immZExt16, CPU64Regs, and>, +def DANDi : ArithLogicI<"andi", uimm16_64, CPU64Regs, immZExt16, and>, ADDI_FM<0xc>; def SLTi64 : SetCC_I<0x0a, "slti", setlt, simm16_64, immSExt16, CPU64Regs>; def SLTiu64 : SetCC_I<0x0b, "sltiu", setult, simm16_64, immSExt16, CPU64Regs>; -def ORi64 : ArithLogicI<"ori", uimm16_64, immZExt16, CPU64Regs, or>, +def ORi64 : ArithLogicI<"ori", uimm16_64, CPU64Regs, immZExt16, or>, ADDI_FM<0xd>; -def XORi64 : ArithLogicI<"xori", uimm16_64, immZExt16, CPU64Regs, xor>, +def XORi64 : ArithLogicI<"xori", uimm16_64, CPU64Regs, immZExt16, xor>, ADDI_FM<0xe>; def LUi64 : LoadUpper<0x0f, "lui", CPU64Regs, uimm16_64>; /// Arithmetic Instructions (3-Operand, R-Type) -def DADD : ArithLogicR<"dadd", IIAlu, CPU64Regs, 1>, ADD_FM<0, 0x2c>; -def DADDu : ArithLogicR<"daddu", IIAlu, CPU64Regs, 1, add>, ADD_FM<0, 0x2d>; -def DSUBu : ArithLogicR<"dsubu", IIAlu, CPU64Regs, 0, sub>, ADD_FM<0, 0x2f>; +def DADD : ArithLogicR<"dadd", CPU64Regs>, ADD_FM<0, 0x2c>; +def DADDu : ArithLogicR<"daddu", CPU64Regs, 1, IIAlu, add>, ADD_FM<0, 0x2d>; +def DSUBu : ArithLogicR<"dsubu", CPU64Regs, 0, IIAlu, sub>, ADD_FM<0, 0x2f>; def SLT64 : SetCC_R<0x00, 0x2a, "slt", setlt, CPU64Regs>; def SLTu64 : SetCC_R<0x00, 0x2b, "sltu", setult, CPU64Regs>; -def AND64 : ArithLogicR<"and", IIAlu, CPU64Regs, 1, and>, ADD_FM<0, 0x24>; -def OR64 : ArithLogicR<"or", IIAlu, CPU64Regs, 1, or>, ADD_FM<0, 0x25>; -def XOR64 : ArithLogicR<"xor", IIAlu, CPU64Regs, 1, xor>, ADD_FM<0, 0x26>; +def AND64 : ArithLogicR<"and", CPU64Regs, 1, IIAlu, and>, ADD_FM<0, 0x24>; +def OR64 : ArithLogicR<"or", CPU64Regs, 1, IIAlu, or>, ADD_FM<0, 0x25>; +def XOR64 : ArithLogicR<"xor", CPU64Regs, 1, IIAlu, xor>, ADD_FM<0, 0x26>; def NOR64 : LogicNOR<0x00, 0x27, "nor", CPU64Regs>; /// Shift Instructions |