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author | Akira Hatanaka <ahatanaka@mips.com> | 2012-12-07 03:06:09 +0000 |
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committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-12-07 03:06:09 +0000 |
commit | 249330eadb9d1d4835d6b55146147840492e5d13 (patch) | |
tree | 790771be97b633ef0d6b65b99e5c485e0beb06bb /lib/Target/Mips/Mips64InstrInfo.td | |
parent | 64ed8e97f75b498a1ba13e08d6c633c75b7f05ec (diff) | |
download | external_llvm-249330eadb9d1d4835d6b55146147840492e5d13.zip external_llvm-249330eadb9d1d4835d6b55146147840492e5d13.tar.gz external_llvm-249330eadb9d1d4835d6b55146147840492e5d13.tar.bz2 |
[mips] Shorten predicate name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169579 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/Mips64InstrInfo.td')
-rw-r--r-- | lib/Target/Mips/Mips64InstrInfo.td | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index 4338279..c76b00b 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -50,23 +50,23 @@ class Div64<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>: multiclass Atomic2Ops64<PatFrag Op, string Opstr> { def #NAME# : Atomic2Ops<Op, Opstr, CPU64Regs, CPURegs>, - Requires<[NotN64, HasStandardEncoding]>; + Requires<[NotN64, HasStdEnc]>; def _P8 : Atomic2Ops<Op, Opstr, CPU64Regs, CPU64Regs>, - Requires<[IsN64, HasStandardEncoding]> { + Requires<[IsN64, HasStdEnc]> { let isCodeGenOnly = 1; } } multiclass AtomicCmpSwap64<PatFrag Op, string Width> { def #NAME# : AtomicCmpSwap<Op, Width, CPU64Regs, CPURegs>, - Requires<[NotN64, HasStandardEncoding]>; + Requires<[NotN64, HasStdEnc]>; def _P8 : AtomicCmpSwap<Op, Width, CPU64Regs, CPU64Regs>, - Requires<[IsN64, HasStandardEncoding]> { + Requires<[IsN64, HasStdEnc]> { let isCodeGenOnly = 1; } } } -let usesCustomInserter = 1, Predicates = [HasStandardEncoding], +let usesCustomInserter = 1, Predicates = [HasStdEnc], DecoderNamespace = "Mips64" in { defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64<atomic_load_add_64, "load_add_64">; defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64<atomic_load_sub_64, "load_sub_64">; @@ -119,7 +119,7 @@ let Pattern = []<dag> in { } } // Rotate Instructions -let Predicates = [HasMips64r2, HasStandardEncoding], +let Predicates = [HasMips64r2, HasStdEnc], DecoderNamespace = "Mips64" in { def DROTR : shift_rotate_imm64<0x3a, 0x01, "drotr", rotr>; def DROTRV : shift_rotate_reg<0x16, 0x01, "drotrv", rotr, CPU64Regs>; @@ -154,15 +154,15 @@ defm SDR : StoreLeftRightM64<0x2d, "sdr", MipsSDR>; /// Load-linked, Store-conditional def LLD : LLBase<0x34, "lld", CPU64Regs, mem>, - Requires<[NotN64, HasStandardEncoding]>; + Requires<[NotN64, HasStdEnc]>; def LLD_P8 : LLBase<0x34, "lld", CPU64Regs, mem64>, - Requires<[IsN64, HasStandardEncoding]> { + Requires<[IsN64, HasStdEnc]> { let isCodeGenOnly = 1; } def SCD : SCBase<0x3c, "scd", CPU64Regs, mem>, - Requires<[NotN64, HasStandardEncoding]>; + Requires<[NotN64, HasStdEnc]>; def SCD_P8 : SCBase<0x3c, "scd", CPU64Regs, mem64>, - Requires<[IsN64, HasStandardEncoding]> { + Requires<[IsN64, HasStdEnc]> { let isCodeGenOnly = 1; } @@ -207,7 +207,7 @@ def LEA_ADDiu64 : EffectiveAddress<0x19,"daddiu\t$rt, $addr", CPU64Regs, mem_ea_ } let Uses = [SP_64], DecoderNamespace = "Mips64" in def DynAlloc64 : EffectiveAddress<0x19,"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>, - Requires<[IsN64, HasStandardEncoding]>; + Requires<[IsN64, HasStdEnc]>; let DecoderNamespace = "Mips64" in { def RDHWR64 : ReadHardware<CPU64Regs, HWRegs64>; @@ -236,13 +236,13 @@ let isCodeGenOnly = 1, rs = 0, shamt = 0 in { //===----------------------------------------------------------------------===// // extended loads -let Predicates = [NotN64, HasStandardEncoding] in { +let Predicates = [NotN64, HasStdEnc] in { def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>; def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>; def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>; def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>; } -let Predicates = [IsN64, HasStandardEncoding] in { +let Predicates = [IsN64, HasStdEnc] in { def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64_P8 addr:$src)>; def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64_P8 addr:$src)>; def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64_P8 addr:$src)>; @@ -295,12 +295,12 @@ defm : SetgeImmPats<CPU64Regs, SLTi64, SLTiu64>; // select MipsDynAlloc def : MipsPat<(MipsDynAlloc addr:$f), (DynAlloc64 addr:$f)>, - Requires<[IsN64, HasStandardEncoding]>; + Requires<[IsN64, HasStdEnc]>; // truncate def : MipsPat<(i32 (trunc CPU64Regs:$src)), (SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>, - Requires<[IsN64, HasStandardEncoding]>; + Requires<[IsN64, HasStdEnc]>; // 32-to-64-bit extension def : MipsPat<(i64 (anyext CPURegs:$src)), (SLL64_32 CPURegs:$src)>; |