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| author | Akira Hatanaka <ahatanaka@mips.com> | 2012-09-15 01:52:08 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-09-15 01:52:08 +0000 |
| commit | 5a7dd43f045f2f78adc81b497c5d78bd9da0884e (patch) | |
| tree | a63e5bf230c6ac226a5776ec7bca13263efa71db /lib/Target/Mips/Mips64InstrInfo.td | |
| parent | 5974c31acbf5368ffc18b23c849d0c823f91f25e (diff) | |
| download | external_llvm-5a7dd43f045f2f78adc81b497c5d78bd9da0884e.zip external_llvm-5a7dd43f045f2f78adc81b497c5d78bd9da0884e.tar.gz external_llvm-5a7dd43f045f2f78adc81b497c5d78bd9da0884e.tar.bz2 | |
Remove aligned/unaligned load/store fragments defined in MipsInstrInfo.td and
use load/store fragments defined in TargetSelectionDAG.td in place of them.
Unaligned loads/stores are either expanded or lowered to target-specific nodes,
so instruction selection should see only aligned load/store nodes.
No changes in functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163960 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/Mips64InstrInfo.td')
| -rw-r--r-- | lib/Target/Mips/Mips64InstrInfo.td | 40 |
1 files changed, 12 insertions, 28 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index 147be5d..fe1e188 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -127,24 +127,15 @@ let DecoderNamespace = "Mips64" in { /// aligned defm LB64 : LoadM64<0x20, "lb", sextloadi8>; defm LBu64 : LoadM64<0x24, "lbu", zextloadi8>; -defm LH64 : LoadM64<0x21, "lh", sextloadi16_a>; -defm LHu64 : LoadM64<0x25, "lhu", zextloadi16_a>; -defm LW64 : LoadM64<0x23, "lw", sextloadi32_a>; -defm LWu64 : LoadM64<0x27, "lwu", zextloadi32_a>; +defm LH64 : LoadM64<0x21, "lh", sextloadi16>; +defm LHu64 : LoadM64<0x25, "lhu", zextloadi16>; +defm LW64 : LoadM64<0x23, "lw", sextloadi32>; +defm LWu64 : LoadM64<0x27, "lwu", zextloadi32>; defm SB64 : StoreM64<0x28, "sb", truncstorei8>; -defm SH64 : StoreM64<0x29, "sh", truncstorei16_a>; -defm SW64 : StoreM64<0x2b, "sw", truncstorei32_a>; -defm LD : LoadM64<0x37, "ld", load_a>; -defm SD : StoreM64<0x3f, "sd", store_a>; - -/// unaligned -defm ULH64 : LoadM64<0x21, "ulh", sextloadi16_u, 1>; -defm ULHu64 : LoadM64<0x25, "ulhu", zextloadi16_u, 1>; -defm ULW64 : LoadM64<0x23, "ulw", sextloadi32_u, 1>; -defm USH64 : StoreM64<0x29, "ush", truncstorei16_u, 1>; -defm USW64 : StoreM64<0x2b, "usw", truncstorei32_u, 1>; -defm ULD : LoadM64<0x37, "uld", load_u, 1>; -defm USD : StoreM64<0x3f, "usd", store_u, 1>; +defm SH64 : StoreM64<0x29, "sh", truncstorei16>; +defm SW64 : StoreM64<0x2b, "sw", truncstorei32>; +defm LD : LoadM64<0x37, "ld", load>; +defm SD : StoreM64<0x3f, "sd", store>; /// load/store left/right let isCodeGenOnly = 1 in { @@ -244,21 +235,14 @@ let isCodeGenOnly = 1, rs = 0, shamt = 0 in { let Predicates = [NotN64, HasStandardEncoding] in { def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>; def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>; - def : MipsPat<(i64 (extloadi16_a addr:$src)), (LH64 addr:$src)>; - def : MipsPat<(i64 (extloadi16_u addr:$src)), (ULH64 addr:$src)>; - def : MipsPat<(i64 (extloadi32_a addr:$src)), (LW64 addr:$src)>; - def : MipsPat<(i64 (extloadi32_u addr:$src)), (ULW64 addr:$src)>; - def : MipsPat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64 addr:$a), 32), 32)>; + def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>; + def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>; } let Predicates = [IsN64, HasStandardEncoding] in { def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64_P8 addr:$src)>; def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64_P8 addr:$src)>; - def : MipsPat<(i64 (extloadi16_a addr:$src)), (LH64_P8 addr:$src)>; - def : MipsPat<(i64 (extloadi16_u addr:$src)), (ULH64_P8 addr:$src)>; - def : MipsPat<(i64 (extloadi32_a addr:$src)), (LW64_P8 addr:$src)>; - def : MipsPat<(i64 (extloadi32_u addr:$src)), (ULW64_P8 addr:$src)>; - def : MipsPat<(zextloadi32_u addr:$a), - (DSRL (DSLL (ULW64_P8 addr:$a), 32), 32)>; + def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64_P8 addr:$src)>; + def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64_P8 addr:$src)>; } // hi/lo relocs |