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| author | Akira Hatanaka <ahatanaka@mips.com> | 2012-12-20 04:13:23 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-12-20 04:13:23 +0000 |
| commit | 5c5402564515ad87425af9881619545c096b84b9 (patch) | |
| tree | 8b8f1663320ba45e7d1e12598eb7cd789770145c /lib/Target/Mips/Mips64InstrInfo.td | |
| parent | 488fdce9821a06732631aececa351ad75a224b19 (diff) | |
| download | external_llvm-5c5402564515ad87425af9881619545c096b84b9.zip external_llvm-5c5402564515ad87425af9881619545c096b84b9.tar.gz external_llvm-5c5402564515ad87425af9881619545c096b84b9.tar.bz2 | |
[mips] Refactor conditional branch instructions with one register operand.
Separate encoding information from the rest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170659 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/Mips64InstrInfo.td')
| -rw-r--r-- | lib/Target/Mips/Mips64InstrInfo.td | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index 7072a1d..9b4b07b 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -168,10 +168,10 @@ def SCD_P8 : SCBase<0x3c, "scd", CPU64Regs, mem64>, def JR64 : IndirectBranch<CPU64Regs>; def BEQ64 : CBranch<"beq", seteq, CPU64Regs>, BEQ_FM<4>; def BNE64 : CBranch<"bne", setne, CPU64Regs>, BEQ_FM<5>; -def BGEZ64 : CBranchZero<0x01, 1, "bgez", setge, CPU64Regs>; -def BGTZ64 : CBranchZero<0x07, 0, "bgtz", setgt, CPU64Regs>; -def BLEZ64 : CBranchZero<0x06, 0, "blez", setle, CPU64Regs>; -def BLTZ64 : CBranchZero<0x01, 0, "bltz", setlt, CPU64Regs>; +def BGEZ64 : CBranchZero<"bgez", setge, CPU64Regs>, BGEZ_FM<1, 1>; +def BGTZ64 : CBranchZero<"bgtz", setgt, CPU64Regs>, BGEZ_FM<7, 0>; +def BLEZ64 : CBranchZero<"blez", setle, CPU64Regs>, BGEZ_FM<6, 0>; +def BLTZ64 : CBranchZero<"bltz", setlt, CPU64Regs>, BGEZ_FM<1, 0>; } let DecoderNamespace = "Mips64" in def JALR64 : JumpLinkReg<0x00, 0x09, "jalr", CPU64Regs>; |