diff options
| author | Akira Hatanaka <ahatanaka@mips.com> | 2012-12-20 04:27:52 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-12-20 04:27:52 +0000 |
| commit | 9bf571fe2c24305aee6a930ed3b2561f6d4ff237 (patch) | |
| tree | ee3861cee93ad8b953d57db752ee7cba74f9f9d2 /lib/Target/Mips/Mips64InstrInfo.td | |
| parent | c23061547de868c5971e1f7a12bc54a37a59a53f (diff) | |
| download | external_llvm-9bf571fe2c24305aee6a930ed3b2561f6d4ff237.zip external_llvm-9bf571fe2c24305aee6a930ed3b2561f6d4ff237.tar.gz external_llvm-9bf571fe2c24305aee6a930ed3b2561f6d4ff237.tar.bz2 | |
[mips] Refactor SLT (set on less than) instructions. Separate encoding
information from the rest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170664 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/Mips64InstrInfo.td')
| -rw-r--r-- | lib/Target/Mips/Mips64InstrInfo.td | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index 0a3a500..39d147f 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -86,8 +86,10 @@ def DADDiu : ArithLogicI<"daddiu", simm16_64, CPU64Regs, immSExt16, add>, ADDI_FM<0x19>, IsAsCheapAsAMove; def DANDi : ArithLogicI<"andi", uimm16_64, CPU64Regs, immZExt16, and>, ADDI_FM<0xc>; -def SLTi64 : SetCC_I<0x0a, "slti", setlt, simm16_64, immSExt16, CPU64Regs>; -def SLTiu64 : SetCC_I<0x0b, "sltiu", setult, simm16_64, immSExt16, CPU64Regs>; +def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, CPU64Regs>, + SLTI_FM<0xa>; +def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, CPU64Regs>, + SLTI_FM<0xb>; def ORi64 : ArithLogicI<"ori", uimm16_64, CPU64Regs, immZExt16, or>, ADDI_FM<0xd>; def XORi64 : ArithLogicI<"xori", uimm16_64, CPU64Regs, immZExt16, xor>, @@ -98,8 +100,8 @@ def LUi64 : LoadUpper<0x0f, "lui", CPU64Regs, uimm16_64>; def DADD : ArithLogicR<"dadd", CPU64Regs>, ADD_FM<0, 0x2c>; def DADDu : ArithLogicR<"daddu", CPU64Regs, 1, IIAlu, add>, ADD_FM<0, 0x2d>; def DSUBu : ArithLogicR<"dsubu", CPU64Regs, 0, IIAlu, sub>, ADD_FM<0, 0x2f>; -def SLT64 : SetCC_R<0x00, 0x2a, "slt", setlt, CPU64Regs>; -def SLTu64 : SetCC_R<0x00, 0x2b, "sltu", setult, CPU64Regs>; +def SLT64 : SetCC_R<"slt", setlt, CPU64Regs>, ADD_FM<0, 0x2a>; +def SLTu64 : SetCC_R<"sltu", setult, CPU64Regs>, ADD_FM<0, 0x2b>; def AND64 : ArithLogicR<"and", CPU64Regs, 1, IIAlu, and>, ADD_FM<0, 0x24>; def OR64 : ArithLogicR<"or", CPU64Regs, 1, IIAlu, or>, ADD_FM<0, 0x25>; def XOR64 : ArithLogicR<"xor", CPU64Regs, 1, IIAlu, xor>, ADD_FM<0, 0x26>; |