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| author | Akira Hatanaka <ahatanaka@mips.com> | 2012-12-20 03:40:03 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-12-20 03:40:03 +0000 |
| commit | ab48c503e231c9a3c9ccccbb57c0a3a7a4302a75 (patch) | |
| tree | ef98b0de7ec3ad3c1b8d8b92308152d250ae0d62 /lib/Target/Mips/Mips64InstrInfo.td | |
| parent | 23a3da0113600a2c3204f766cbc51d68a8ed4d94 (diff) | |
| download | external_llvm-ab48c503e231c9a3c9ccccbb57c0a3a7a4302a75.zip external_llvm-ab48c503e231c9a3c9ccccbb57c0a3a7a4302a75.tar.gz external_llvm-ab48c503e231c9a3c9ccccbb57c0a3a7a4302a75.tar.bz2 | |
[mips] Refactor arithmetic and logic instructions with immediate operands.
Separate encoding information from the rest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170648 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/Mips64InstrInfo.td')
| -rw-r--r-- | lib/Target/Mips/Mips64InstrInfo.td | 22 |
1 files changed, 13 insertions, 9 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index dde7bc6..d36d1ff 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -83,15 +83,19 @@ let usesCustomInserter = 1, Predicates = [HasStdEnc], //===----------------------------------------------------------------------===// let DecoderNamespace = "Mips64" in { /// Arithmetic Instructions (ALU Immediate) -def DADDi : ArithLogicI<0x18, "daddi", simm16_64, immSExt16, CPU64Regs>; -def DADDiu : ArithLogicI<0x19, "daddiu", simm16_64, immSExt16, CPU64Regs, - add>, IsAsCheapAsAMove; -def DANDi : ArithLogicI<0x0c, "andi", uimm16_64, immZExt16, CPU64Regs, and>; -def SLTi64 : SetCC_I<0x0a, "slti", setlt, simm16_64, immSExt16, CPU64Regs>; -def SLTiu64 : SetCC_I<0x0b, "sltiu", setult, simm16_64, immSExt16, CPU64Regs>; -def ORi64 : ArithLogicI<0x0d, "ori", uimm16_64, immZExt16, CPU64Regs, or>; -def XORi64 : ArithLogicI<0x0e, "xori", uimm16_64, immZExt16, CPU64Regs, xor>; -def LUi64 : LoadUpper<0x0f, "lui", CPU64Regs, uimm16_64>; +def DADDi : ArithLogicI<"daddi", simm16_64, immSExt16, CPU64Regs>, + ADDI_FM<0x18>; +def DADDiu : ArithLogicI<"daddiu", simm16_64, immSExt16, CPU64Regs, add>, + ADDI_FM<0x19>, IsAsCheapAsAMove; +def DANDi : ArithLogicI<"andi", uimm16_64, immZExt16, CPU64Regs, and>, + ADDI_FM<0xc>; +def SLTi64 : SetCC_I<0x0a, "slti", setlt, simm16_64, immSExt16, CPU64Regs>; +def SLTiu64 : SetCC_I<0x0b, "sltiu", setult, simm16_64, immSExt16, CPU64Regs>; +def ORi64 : ArithLogicI<"ori", uimm16_64, immZExt16, CPU64Regs, or>, + ADDI_FM<0xd>; +def XORi64 : ArithLogicI<"xori", uimm16_64, immZExt16, CPU64Regs, xor>, + ADDI_FM<0xe>; +def LUi64 : LoadUpper<0x0f, "lui", CPU64Regs, uimm16_64>; /// Arithmetic Instructions (3-Operand, R-Type) def DADD : ArithLogicR<"dadd", IIAlu, CPU64Regs, 1>, ADD_FM<0, 0x2c>; |