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| author | Jack Carter <jcarter@mips.com> | 2012-07-16 15:14:51 +0000 |
|---|---|---|
| committer | Jack Carter <jcarter@mips.com> | 2012-07-16 15:14:51 +0000 |
| commit | e035f65b16956cdb7ba29e741b7e3c04a8ce4d24 (patch) | |
| tree | ea58432ec6155317779d6adabcc181ccebb68180 /lib/Target/Mips/Mips64InstrInfo.td | |
| parent | 694fbf17777f96e65e782667826dbccbe7524c32 (diff) | |
| download | external_llvm-e035f65b16956cdb7ba29e741b7e3c04a8ce4d24.zip external_llvm-e035f65b16956cdb7ba29e741b7e3c04a8ce4d24.tar.gz external_llvm-e035f65b16956cdb7ba29e741b7e3c04a8ce4d24.tar.bz2 | |
Doubleword Shift Left Logical Plus 32
Mips shift instructions DSLL, DSRL and DSRA are transformed into
DSLL32, DSRL32 and DSRA32 respectively if the shift amount is between
32 and 63
Here is a description of DSLL:
Purpose: Doubleword Shift Left Logical Plus 32
To execute a left-shift of a doubleword by a fixed amount--32 to 63 bits
Description: GPR[rd] <- GPR[rt] << (sa+32)
The 64-bit doubleword contents of GPR rt are shifted left, inserting
zeros into the emptied bits; the result is placed in
GPR rd. The bit-shift amount in the range 0 to 31 is specified by sa.
This patch implements the direct object output of these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160277 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/Mips64InstrInfo.td')
| -rw-r--r-- | lib/Target/Mips/Mips64InstrInfo.td | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index 7a9d41b..cceee24 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -109,6 +109,11 @@ def DSRA : shift_rotate_imm64<0x3b, 0x00, "dsra", sra>; def DSLLV : shift_rotate_reg<0x14, 0x00, "dsllv", shl, CPU64Regs>; def DSRLV : shift_rotate_reg<0x16, 0x00, "dsrlv", srl, CPU64Regs>; def DSRAV : shift_rotate_reg<0x17, 0x00, "dsrav", sra, CPU64Regs>; +let Pattern = []<dag> in { +def DSLL32 : shift_rotate_imm64<0x3c, 0x00, "dsll32", shl>; +def DSRL32 : shift_rotate_imm64<0x3e, 0x00, "dsrl32", srl>; +def DSRA32 : shift_rotate_imm64<0x3f, 0x00, "dsra32", sra>; +} } // Rotate Instructions let Predicates = [HasMips64r2, HasStandardEncoding], |