diff options
| author | Akira Hatanaka <ahatanaka@mips.com> | 2012-12-21 23:17:36 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-12-21 23:17:36 +0000 |
| commit | e8bc10b902f15eb4a12b810d5ab06a2755e7f990 (patch) | |
| tree | ee1213fa3931936edbe0455e1519cb0ec2ab05af /lib/Target/Mips/Mips64InstrInfo.td | |
| parent | aa7c9cd1814ad080c7f8e5c2c4434c206e0ea66d (diff) | |
| download | external_llvm-e8bc10b902f15eb4a12b810d5ab06a2755e7f990.zip external_llvm-e8bc10b902f15eb4a12b810d5ab06a2755e7f990.tar.gz external_llvm-e8bc10b902f15eb4a12b810d5ab06a2755e7f990.tar.bz2 | |
[mips] Refactor SYNC and multiply/divide instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170955 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/Mips64InstrInfo.td')
| -rw-r--r-- | lib/Target/Mips/Mips64InstrInfo.td | 16 |
1 files changed, 6 insertions, 10 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index 2f1e7ec..4a9d94f6 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -40,12 +40,6 @@ let DecoderNamespace = "Mips64" in { class shift_rotate_imm64<string opstr, SDPatternOperator OpNode = null_frag>: shift_rotate_imm<opstr, immZExt6, shamt, CPU64Regs, OpNode>; -// Mul, Div -class Mult64<bits<6> func, string instr_asm, InstrItinClass itin>: - Mult<func, instr_asm, itin, CPU64Regs, [HI64, LO64]>; -class Div64<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>: - Div<op, func, instr_asm, itin, CPU64Regs, [HI64, LO64]>; - multiclass Atomic2Ops64<PatFrag Op> { def #NAME# : Atomic2Ops<Op, CPU64Regs, CPURegs>, Requires<[NotN64, HasStdEnc]>; @@ -178,10 +172,12 @@ def TAILCALL64_R : JumpFR<CPU64Regs, MipsTailCall>, MTLO_FM<8>, IsTailCall; let DecoderNamespace = "Mips64" in { /// Multiply and Divide Instructions. -def DMULT : Mult64<0x1c, "dmult", IIImul>; -def DMULTu : Mult64<0x1d, "dmultu", IIImul>; -def DSDIV : Div64<MipsDivRem, 0x1e, "ddiv", IIIdiv>; -def DUDIV : Div64<MipsDivRemU, 0x1f, "ddivu", IIIdiv>; +def DMULT : Mult<"dmult", IIImul, CPU64Regs, [HI64, LO64]>, MULT_FM<0, 0x1c>; +def DMULTu : Mult<"dmultu", IIImul, CPU64Regs, [HI64, LO64]>, MULT_FM<0, 0x1d>; +def DSDIV : Div<MipsDivRem, "ddiv", IIIdiv, CPU64Regs, [HI64, LO64]>, + MULT_FM<0, 0x1e>; +def DUDIV : Div<MipsDivRemU, "ddivu", IIIdiv, CPU64Regs, [HI64, LO64]>, + MULT_FM<0, 0x1f>; def MTHI64 : MoveToLOHI<"mthi", CPU64Regs, [HI64]>, MTLO_FM<0x11>; def MTLO64 : MoveToLOHI<"mtlo", CPU64Regs, [LO64]>, MTLO_FM<0x13>; |