Merge with LLVM upstream r144606 (Nov 15th 2011)

Conflicts:
	Makefile.rules
	configure
	docs/ReleaseNotes.html
	lib/Analysis/ScalarEvolution.cpp
	lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
	lib/CodeGen/ExecutionDepsFix.cpp
	lib/CodeGen/MachineBlockPlacement.cpp
	lib/CodeGen/MachineBranchProbabilityInfo.cpp
	lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
	lib/ExecutionEngine/JIT/LLVMBuild.txt
	lib/MC/LLVMBuild.txt
	lib/MC/MCDisassembler/LLVMBuild.txt
	lib/MC/MCDwarf.cpp
	lib/Object/LLVMBuild.txt
	lib/Target/ARM/ARMExpandPseudoInsts.cpp
	lib/Target/ARM/ARMFastISel.cpp
	lib/Target/ARM/ARMInstrInfo.td
	lib/Target/ARM/AsmParser/ARMAsmParser.cpp
	lib/Target/ARM/Disassembler/ARMDisassembler.cpp
	lib/Target/ARM/Disassembler/LLVMBuild.txt
	lib/Target/ARM/TargetInfo/LLVMBuild.txt
	lib/Target/CBackend/TargetInfo/LLVMBuild.txt
	lib/Target/CellSPU/MCTargetDesc/LLVMBuild.txt
	lib/Target/CellSPU/TargetInfo/LLVMBuild.txt
	lib/Target/CppBackend/TargetInfo/LLVMBuild.txt
	lib/Target/LLVMBuild.txt
	lib/Target/MBlaze/Disassembler/LLVMBuild.txt
	lib/Target/MBlaze/TargetInfo/LLVMBuild.txt
	lib/Target/MSP430/MCTargetDesc/LLVMBuild.txt
	lib/Target/MSP430/TargetInfo/LLVMBuild.txt
	lib/Target/Mips/CMakeLists.txt
	lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp
	lib/Target/Mips/Mips64InstrInfo.td
	lib/Target/Mips/MipsAsmPrinter.cpp
	lib/Target/Mips/MipsISelLowering.cpp
	lib/Target/Mips/MipsMCInstLower.cpp
	lib/Target/Mips/TargetInfo/LLVMBuild.txt
	lib/Target/PTX/LLVMBuild.txt
	lib/Target/PTX/PTXAsmPrinter.cpp
	lib/Target/PTX/TargetInfo/LLVMBuild.txt
	lib/Target/PowerPC/TargetInfo/LLVMBuild.txt
	lib/Target/Sparc/TargetInfo/LLVMBuild.txt
	lib/Target/X86/TargetInfo/LLVMBuild.txt
	lib/Target/X86/X86ISelLowering.cpp
	lib/Target/X86/X86InstrSSE.td
	lib/Target/XCore/MCTargetDesc/LLVMBuild.txt
	lib/Target/XCore/TargetInfo/LLVMBuild.txt
	lib/Transforms/IPO/LLVMBuild.txt
	lib/Transforms/Utils/LLVMBuild.txt
	test/CodeGen/ARM/2011-10-26-memset-with-neon.ll
	test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll
	test/CodeGen/ARM/fast-isel-cmp-imm.ll
	test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll
	test/CodeGen/CellSPU/call_indirect.ll
	test/CodeGen/X86/avx2-logic.ll
	test/CodeGen/X86/block-placement.ll
	test/CodeGen/X86/sse-domains.ll
	test/CodeGen/X86/sse3.ll
	test/CodeGen/X86/vec_shuffle-39.ll
	test/MC/ARM/neon-vld-encoding.s
	test/MC/ARM/neon-vst-encoding.s
	tools/llvm-config-2/llvm-config.cpp
	utils/TableGen/LLVMBuild.txt

Change-Id: I70f454db6fc79d7799f56d0f6f2eb7b99561c504

1 files changed, 22 insertions, 2 deletions

diff --git a/lib/Target/Mips/MipsFrameLowering.cpp b/lib/Target/Mips/MipsFrameLowering.cpp
index 71f3116..19bb1a5 100644
--- a/lib/Target/Mips/MipsFrameLowering.cpp
+++ b/lib/Target/Mips/MipsFrameLowering.cpp
@@ -14,6 +14,7 @@
 #include "MipsFrameLowering.h"
 #include "MipsInstrInfo.h"
 #include "MipsMachineFunction.h"
+#include "MCTargetDesc/MipsBaseInfo.h"
 #include "llvm/Function.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
@@ -149,6 +150,11 @@ void MipsFrameLowering::emitPrologue(MachineFunction &MF) const {
   unsigned NewReg = 0;
   int NewImm = 0;
   bool ATUsed;
+  unsigned GP = STI.isABI_N64() ? Mips::GP_64 : Mips::GP;
+  unsigned T9 = STI.isABI_N64() ? Mips::T9_64 : Mips::T9;
+  unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
+  unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
+  unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
 
   // First, compute final stack size.
   unsigned RegSize = STI.isGP32bit() ? 4 : 8;
@@ -157,7 +163,6 @@ void MipsFrameLowering::emitPrologue(MachineFunction &MF) const {
     (MFI->getObjectOffset(MipsFI->getGPFI()) + RegSize) :
     MipsFI->getMaxCallFrameSize();
   unsigned StackSize = AlignOffset(LocalVarAreaOffset, StackAlign) +
-    AlignOffset(MipsFI->getRegSaveAreaSize(), StackAlign) +
     AlignOffset(MFI->getStackSize(), StackAlign);
 
    // Update stack size
@@ -165,10 +170,25 @@ void MipsFrameLowering::emitPrologue(MachineFunction &MF) const {
   
   BuildMI(MBB, MBBI, dl, TII.get(Mips::NOREORDER));
 
-  // TODO: check need from GP here.
+  // Emit instructions that set $gp using the the value of $t9.
+  // O32 uses the directive .cpload while N32/64 requires three instructions to
+  // do this.  
+  // TODO: Do not emit these instructions if no instructions use $gp.
   if (isPIC && STI.isABI_O32())
     BuildMI(MBB, MBBI, dl, TII.get(Mips::CPLOAD))
       .addReg(RegInfo->getPICCallReg());
+  else if (STI.isABI_N64() || (isPIC && STI.isABI_N32())) {
+    //  lui     $28,%hi(%neg(%gp_rel(fname)))
+    //  addu    $28,$28,$25
+    //  addiu   $28,$28,%lo(%neg(%gp_rel(fname)))
+    const GlobalValue *FName = MF.getFunction();
+    BuildMI(MBB, MBBI, dl, TII.get(LUi), GP)
+      .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
+    BuildMI(MBB, MBBI, dl, TII.get(ADDu), GP).addReg(GP).addReg(T9);
+    BuildMI(MBB, MBBI, dl, TII.get(ADDiu), GP).addReg(GP)
+      .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
+  }
+
   BuildMI(MBB, MBBI, dl, TII.get(Mips::NOMACRO));
 
   // No need to allocate space on the stack.