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authorChad Rosier <mcrosier@apple.com>2013-06-22 18:37:38 +0000
committerChad Rosier <mcrosier@apple.com>2013-06-22 18:37:38 +0000
commit5b3fca50a08865f0db55fc92ad1c037a04e12177 (patch)
tree998e3b634ae4bbd2829c36ff98b0fa70e3cda198 /lib/Target/Mips/MipsISelLowering.cpp
parent5729b8ea01739cf9b1171f0a4349275bc8124756 (diff)
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The getRegForInlineAsmConstraint function should only accept MVT value types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184642 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsISelLowering.cpp')
-rw-r--r--lib/Target/Mips/MipsISelLowering.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp
index 6351073..a58f177 100644
--- a/lib/Target/Mips/MipsISelLowering.cpp
+++ b/lib/Target/Mips/MipsISelLowering.cpp
@@ -2885,7 +2885,7 @@ MipsTargetLowering::getSingleConstraintMatchWeight(
/// to an LLVM register class, return a register of 0 and the register class
/// pointer.
std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
-getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
+getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
{
if (Constraint.size() == 1) {
switch (Constraint[0]) {