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author | Akira Hatanaka <ahatanaka@mips.com> | 2013-03-05 22:41:55 +0000 |
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committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-03-05 22:41:55 +0000 |
commit | 7433b2e1142a46c1dbb491d91e0175cb9ce83167 (patch) | |
tree | acef571deefef6c7b3c8e93a17be13d5c333e814 /lib/Target/Mips/MipsISelLowering.h | |
parent | cb2eafdfa358ae8a1e1f9ae39d8c72cd4d446da1 (diff) | |
download | external_llvm-7433b2e1142a46c1dbb491d91e0175cb9ce83167.zip external_llvm-7433b2e1142a46c1dbb491d91e0175cb9ce83167.tar.gz external_llvm-7433b2e1142a46c1dbb491d91e0175cb9ce83167.tar.bz2 |
[mips] Fix MipsTargetLowering::LowerCallResult and LowerReturn to correctly
handle fp128 returns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176523 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsISelLowering.h')
-rw-r--r-- | lib/Target/Mips/MipsISelLowering.h | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h index ee40232..4424521 100644 --- a/lib/Target/Mips/MipsISelLowering.h +++ b/lib/Target/Mips/MipsISelLowering.h @@ -211,6 +211,14 @@ namespace llvm { void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, bool IsSoftFloat, Function::const_arg_iterator FuncArg); + + void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, + bool IsSoftFloat, const SDNode *CallNode, + const Type *RetTy) const; + + void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, + bool IsSoftFloat, const Type *RetTy) const; + const CCState &getCCInfo() const { return CCInfo; } /// hasByValArg - Returns true if function has byval arguments. @@ -260,6 +268,10 @@ namespace llvm { MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode, bool IsSoftFloat) const; + template<typename Ty> + void analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat, + const SDNode *CallNode, const Type *RetTy) const; + CCState &CCInfo; CallingConv::ID CallConv; bool IsO32; @@ -276,7 +288,8 @@ namespace llvm { CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, - SmallVectorImpl<SDValue> &InVals) const; + SmallVectorImpl<SDValue> &InVals, + const SDNode *CallNode, const Type *RetTy) const; // Lower Operand specifics SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; |