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author | Akira Hatanaka <ahatanaka@mips.com> | 2012-12-13 01:24:00 +0000 |
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committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-12-13 01:24:00 +0000 |
commit | 6f94eb3512ebc7b279451d26427153d9300a6a14 (patch) | |
tree | 1c8d0947f9ba98d4b0c78a882cbb262bb118ca24 /lib/Target/Mips/MipsInstrFPU.td | |
parent | be9f72d2d8ab4a785cf788c5d9c5092b0fc02bfc (diff) | |
download | external_llvm-6f94eb3512ebc7b279451d26427153d9300a6a14.zip external_llvm-6f94eb3512ebc7b279451d26427153d9300a6a14.tar.gz external_llvm-6f94eb3512ebc7b279451d26427153d9300a6a14.tar.bz2 |
[mips] Modify definitions of floating point load and store instructions.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170072 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsInstrFPU.td')
-rw-r--r-- | lib/Target/Mips/MipsInstrFPU.td | 33 |
1 files changed, 23 insertions, 10 deletions
diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td index b1a836e..da1d207 100644 --- a/lib/Target/Mips/MipsInstrFPU.td +++ b/lib/Target/Mips/MipsInstrFPU.td @@ -234,6 +234,19 @@ class MTC1_FT<string opstr, RegisterClass DstRC, RegisterClass SrcRC, InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"), [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR>; +class LW_FT<string opstr, RegisterClass RC, InstrItinClass Itin, + Operand MemOpnd, SDPatternOperator OpNode= null_frag> : + InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), + [(set RC:$rt, (OpNode addr:$addr))], Itin, FrmFI> { + let DecoderMethod = "DecodeFMem"; +} + +class SW_FT<string opstr, RegisterClass RC, InstrItinClass Itin, + Operand MemOpnd, SDPatternOperator OpNode= null_frag> : + InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), + [(OpNode RC:$rt, addr:$addr)], Itin, FrmFI> { + let DecoderMethod = "DecodeFMem"; +} //===----------------------------------------------------------------------===// // Floating Point Instructions @@ -328,30 +341,30 @@ def FMOV_D64 : ABSS_FT<"mov.d", FGR64, FGR64, IIFmove>, ABSS_FM<0x6, 17>, /// Floating Point Memory Instructions let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in { - def LWC1_P8 : FPLoad<0x31, "lwc1", FGR32, mem64>; - def SWC1_P8 : FPStore<0x39, "swc1", FGR32, mem64>; - def LDC164_P8 : FPLoad<0x35, "ldc1", FGR64, mem64> { + def LWC1_P8 : LW_FT<"lwc1", FGR32, IILoad, mem64, load>, LW_FM<0x31>; + def SWC1_P8 : SW_FT<"swc1", FGR32, IIStore, mem64, store>, LW_FM<0x39>; + def LDC164_P8 : LW_FT<"ldc1", FGR64, IILoad, mem64, load>, LW_FM<0x35> { let isCodeGenOnly =1; } - def SDC164_P8 : FPStore<0x3d, "sdc1", FGR64, mem64> { + def SDC164_P8 : SW_FT<"sdc1", FGR64, IIStore, mem64, store>, LW_FM<0x3d> { let isCodeGenOnly =1; } } let Predicates = [NotN64, HasStdEnc] in { - def LWC1 : FPLoad<0x31, "lwc1", FGR32, mem>; - def SWC1 : FPStore<0x39, "swc1", FGR32, mem>; + def LWC1 : LW_FT<"lwc1", FGR32, IILoad, mem, load>, LW_FM<0x31>; + def SWC1 : SW_FT<"swc1", FGR32, IIStore, mem, store>, LW_FM<0x39>; } let Predicates = [NotN64, HasMips64, HasStdEnc], DecoderNamespace = "Mips64" in { - def LDC164 : FPLoad<0x35, "ldc1", FGR64, mem>; - def SDC164 : FPStore<0x3d, "sdc1", FGR64, mem>; + def LDC164 : LW_FT<"ldc1", FGR64, IILoad, mem, load>, LW_FM<0x35>; + def SDC164 : SW_FT<"sdc1", FGR64, IIStore, mem, store>, LW_FM<0x3d>; } let Predicates = [NotN64, NotMips64, HasStdEnc] in { - def LDC1 : FPLoad<0x35, "ldc1", AFGR64, mem>; - def SDC1 : FPStore<0x3d, "sdc1", AFGR64, mem>; + def LDC1 : LW_FT<"ldc1", AFGR64, IILoad, mem, load>, LW_FM<0x35>; + def SDC1 : SW_FT<"sdc1", AFGR64, IIStore, mem, store>, LW_FM<0x3d>; } // Indexed loads and stores. |