diff options
author | Jia Liu <proljc@gmail.com> | 2012-02-28 07:46:26 +0000 |
---|---|---|
committer | Jia Liu <proljc@gmail.com> | 2012-02-28 07:46:26 +0000 |
commit | bb481f882093fb738d2bb15610c79364bada5496 (patch) | |
tree | b7576c5dfdd780ee43fd00ca3fd5a76a608fa7bd /lib/Target/Mips/MipsInstrFPU.td | |
parent | ec52aaa12f57896fc806e849fa21a61603050ac4 (diff) | |
download | external_llvm-bb481f882093fb738d2bb15610c79364bada5496.zip external_llvm-bb481f882093fb738d2bb15610c79364bada5496.tar.gz external_llvm-bb481f882093fb738d2bb15610c79364bada5496.tar.bz2 |
remove blanks, and some code format
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151625 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsInstrFPU.td')
-rw-r--r-- | lib/Target/Mips/MipsInstrFPU.td | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td index 46fd278..cb97a50 100644 --- a/lib/Target/Mips/MipsInstrFPU.td +++ b/lib/Target/Mips/MipsInstrFPU.td @@ -1,4 +1,4 @@ -//===- MipsInstrFPU.td - Mips FPU Instruction Information --*- tablegen -*-===// +//===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===// // // The LLVM Compiler Infrastructure // @@ -267,12 +267,12 @@ let Predicates = [HasMips32r2Or64] in { } let Predicates = [HasMips32r2, NotMips64] in { - def LDXC1 : FPIdxLoad<0x1, "ldxc1", AFGR64, CPURegs, load_a>; + def LDXC1 : FPIdxLoad<0x1, "ldxc1", AFGR64, CPURegs, load_a>; def SDXC1 : FPIdxStore<0x9, "sdxc1", AFGR64, CPURegs, store_a>; } let Predicates = [HasMips64, NotN64] in { - def LDXC164 : FPIdxLoad<0x1, "ldxc1", FGR64, CPURegs, load_a>; + def LDXC164 : FPIdxLoad<0x1, "ldxc1", FGR64, CPURegs, load_a>; def SDXC164 : FPIdxStore<0x9, "sdxc1", FGR64, CPURegs, store_a>; } @@ -280,7 +280,7 @@ let Predicates = [HasMips64, NotN64] in { let Predicates = [IsN64] in { def LWXC1_P8 : FPIdxLoad<0x0, "lwxc1", FGR32, CPU64Regs, load_a>; def LUXC1_P8 : FPIdxLoad<0x5, "luxc1", FGR32, CPU64Regs, load_u>; - def LDXC164_P8 : FPIdxLoad<0x1, "ldxc1", FGR64, CPU64Regs, load_a>; + def LDXC164_P8 : FPIdxLoad<0x1, "ldxc1", FGR64, CPU64Regs, load_a>; def SWXC1_P8 : FPIdxStore<0x8, "swxc1", FGR32, CPU64Regs, store_a>; def SUXC1_P8 : FPIdxStore<0xd, "suxc1", FGR32, CPU64Regs, store_u>; def SDXC164_P8 : FPIdxStore<0x9, "sdxc1", FGR64, CPU64Regs, store_a>; |