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author | Akira Hatanaka <ahatanaka@mips.com> | 2012-03-01 22:12:30 +0000 |
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committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-03-01 22:12:30 +0000 |
commit | dfa27aea12ae1d69a7e94ed5e6df6be1cc90d9e3 (patch) | |
tree | a4992878fc2d7e2979d50e6e295b0ab5b162fa4b /lib/Target/Mips/MipsInstrFPU.td | |
parent | 97e910ecff5ed8b653a07fb1d014dab772931c0b (diff) | |
download | external_llvm-dfa27aea12ae1d69a7e94ed5e6df6be1cc90d9e3.zip external_llvm-dfa27aea12ae1d69a7e94ed5e6df6be1cc90d9e3.tar.gz external_llvm-dfa27aea12ae1d69a7e94ed5e6df6be1cc90d9e3.tar.bz2 |
Fix bugs which were introduced when support for base+index floating point loads
and stores was added.
- SelectAddr should return false if Parent is an unaligned f32 load or store.
- Only aligned load and store nodes should be matched to select reg+imm
floating point instructions.
- MIPS does not have support for f64 unaligned load or store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151843 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsInstrFPU.td')
-rw-r--r-- | lib/Target/Mips/MipsInstrFPU.td | 17 |
1 files changed, 15 insertions, 2 deletions
diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td index cb97a50..fe5eaec 100644 --- a/lib/Target/Mips/MipsInstrFPU.td +++ b/lib/Target/Mips/MipsInstrFPU.td @@ -85,13 +85,13 @@ def fpimm0neg : PatLeaf<(fpimm), [{ // FP load. class FPLoad<bits<6> op, string opstr, RegisterClass RC, Operand MemOpnd>: FMem<op, (outs RC:$ft), (ins MemOpnd:$addr), - !strconcat(opstr, "\t$ft, $addr"), [(set RC:$ft, (load addr:$addr))], + !strconcat(opstr, "\t$ft, $addr"), [(set RC:$ft, (load_a addr:$addr))], IILoad>; // FP store. class FPStore<bits<6> op, string opstr, RegisterClass RC, Operand MemOpnd>: FMem<op, (outs), (ins RC:$ft, MemOpnd:$addr), - !strconcat(opstr, "\t$ft, $addr"), [(store RC:$ft, addr:$addr)], + !strconcat(opstr, "\t$ft, $addr"), [(store_a RC:$ft, addr:$addr)], IIStore>; // FP indexed load. @@ -433,3 +433,16 @@ let Predicates = [IsFP64bit] in { def : Pat<(f32 (fround FGR64:$src)), (CVT_S_D64 FGR64:$src)>; def : Pat<(f64 (fextend FGR32:$src)), (CVT_D64_S FGR32:$src)>; } + +// Patterns for unaligned floating point loads and stores. +let Predicates = [HasMips32r2Or64, NotN64] in { + def : Pat<(f32 (load_u CPURegs:$addr)), (LUXC1 CPURegs:$addr, ZERO)>; + def : Pat<(store_u FGR32:$src, CPURegs:$addr), + (SUXC1 FGR32:$src, CPURegs:$addr, ZERO)>; +} + +let Predicates = [IsN64] in { + def : Pat<(f32 (load_u CPU64Regs:$addr)), (LUXC1_P8 CPU64Regs:$addr, ZERO_64)>; + def : Pat<(store_u FGR32:$src, CPU64Regs:$addr), + (SUXC1_P8 FGR32:$src, CPU64Regs:$addr, ZERO_64)>; +} |