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author | Vladimir Medic <Vladimir.Medic@imgtec.com> | 2013-09-06 13:08:00 +0000 |
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committer | Vladimir Medic <Vladimir.Medic@imgtec.com> | 2013-09-06 13:08:00 +0000 |
commit | 638382e6f169649eb86fa47a6ea25dd932f07689 (patch) | |
tree | 07526bd2d49ea0ecd7b91d5a3398d478280da78c /lib/Target/Mips/MipsInstrInfo.td | |
parent | 3aaa3e31aa35164fa54474bcf3a2c2df5ab8b375 (diff) | |
download | external_llvm-638382e6f169649eb86fa47a6ea25dd932f07689.zip external_llvm-638382e6f169649eb86fa47a6ea25dd932f07689.tar.gz external_llvm-638382e6f169649eb86fa47a6ea25dd932f07689.tar.bz2 |
This patch adds support for microMIPS Multiply and Add/Sub instructions. Test cases are included in patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190154 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsInstrInfo.td')
-rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 9929334..d7396e3 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -413,7 +413,7 @@ class ArithLogicI<string opstr, Operand Od, RegisterOperand RO, // Arithmetic Multiply ADD/SUB class MArithR<string opstr, bit isComm = 0> : InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt), - !strconcat(opstr, "\t$rs, $rt"), [], IIImult, FrmR> { + !strconcat(opstr, "\t$rs, $rt"), [], IIImult, FrmR, opstr> { let Defs = [HI0, LO0]; let Uses = [HI0, LO0]; let isCommutable = isComm; @@ -1044,10 +1044,10 @@ def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>; def LEA_ADDiu : EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>; // MADD*/MSUB* -def MADD : MArithR<"madd", 1>, MULT_FM<0x1c, 0>; -def MADDU : MArithR<"maddu", 1>, MULT_FM<0x1c, 1>; -def MSUB : MArithR<"msub">, MULT_FM<0x1c, 4>; -def MSUBU : MArithR<"msubu">, MULT_FM<0x1c, 5>; +def MADD : MMRel, MArithR<"madd", 1>, MULT_FM<0x1c, 0>; +def MADDU : MMRel, MArithR<"maddu", 1>, MULT_FM<0x1c, 1>; +def MSUB : MMRel, MArithR<"msub">, MULT_FM<0x1c, 4>; +def MSUBU : MMRel, MArithR<"msubu">, MULT_FM<0x1c, 5>; def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd>; def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu>; def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub>; |