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author | Reed Kotler <rkotler@mips.com> | 2012-10-28 06:02:37 +0000 |
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committer | Reed Kotler <rkotler@mips.com> | 2012-10-28 06:02:37 +0000 |
commit | f99998a2b0a6c186b3a1b6ad7bfa488009a0c5f5 (patch) | |
tree | 84974b0efbe886c97e619015aa85e79164088863 /lib/Target/Mips/MipsMachineFunction.h | |
parent | 163f67f4d98aab114cb9b04efd086f54f7688d0c (diff) | |
download | external_llvm-f99998a2b0a6c186b3a1b6ad7bfa488009a0c5f5.zip external_llvm-f99998a2b0a6c186b3a1b6ad7bfa488009a0c5f5.tar.gz external_llvm-f99998a2b0a6c186b3a1b6ad7bfa488009a0c5f5.tar.bz2 |
This patch is for the implementation of mips16 complex pattern addr16.
Previously mips16 was sharing the pattern addr which is used for mips32
and mips64. This had a number of problems:
1) Storing and loading byte and halfword quantities for mips16 has particular
problems due to the primarily non mips16 nature of SP. When we must
load/store byte/halfword stack objects in a function, we must create a mips16
alias register for SP. This functionality is tested in stchar.ll.
2) We need to have an FP register under certain conditions (such as
dynamically sized alloca). We use mips16 register S0 for this purpose.
In this case, we also use this register when accessing frame objects so this
issue also affects the complex pattern addr16. This functionality is
tested in alloca16.ll.
The Mips16InstrInfo.td has been updated to use addr16 instead of addr.
The complex pattern C++ function for addr has been copied to addr16 and
updated to reflect the above issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166897 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsMachineFunction.h')
-rw-r--r-- | lib/Target/Mips/MipsMachineFunction.h | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/lib/Target/Mips/MipsMachineFunction.h b/lib/Target/Mips/MipsMachineFunction.h index b05f618..f9efe07 100644 --- a/lib/Target/Mips/MipsMachineFunction.h +++ b/lib/Target/Mips/MipsMachineFunction.h @@ -39,6 +39,11 @@ class MipsFunctionInfo : public MachineFunctionInfo { /// relocation models. unsigned GlobalBaseReg; + /// Mips16SPAliasReg - keeps track of the virtual register initialized for + /// use as an alias for SP for use in load/store of halfword/byte from/to + /// the stack + unsigned Mips16SPAliasReg; + /// VarArgsFrameIndex - FrameIndex for start of varargs area. int VarArgsFrameIndex; @@ -46,8 +51,8 @@ class MipsFunctionInfo : public MachineFunctionInfo { public: MipsFunctionInfo(MachineFunction& MF) - : MF(MF), SRetReturnReg(0), GlobalBaseReg(0), - VarArgsFrameIndex(0), EmitNOAT(false) + : MF(MF), SRetReturnReg(0), GlobalBaseReg(0), Mips16SPAliasReg(0), + VarArgsFrameIndex(0), EmitNOAT(false) {} unsigned getSRetReturnReg() const { return SRetReturnReg; } @@ -56,6 +61,9 @@ public: bool globalBaseRegSet() const; unsigned getGlobalBaseReg(); + bool mips16SPAliasRegSet() const; + unsigned getMips16SPAliasReg(); + int getVarArgsFrameIndex() const { return VarArgsFrameIndex; } void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; } |