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authorJakob Stoklund Olesen <stoklund@2pi.dk>2011-06-09 16:56:59 +0000
committerJakob Stoklund Olesen <stoklund@2pi.dk>2011-06-09 16:56:59 +0000
commit2a9d1ca9c244aeac98044a5fc9a081ff3df7b2ff (patch)
tree49d18cc72723705aed0596cb965ecbd9942cff51 /lib/Target/Mips/MipsRegisterInfo.cpp
parent6f3661fdcd10a33d225502f8b112dc5b7968ef74 (diff)
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Remove custom allocation order boilerplate that is no longer needed.
The register allocators automatically filter out reserved registers and place the callee saved registers last in the allocation order, so custom methods are no longer necessary just for that. Some targets still use custom allocation orders: ARM/Thumb: The high registers are removed from GPR in thumb mode. The NEON allocation orders prefer to use non-VFP2 registers first. X86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble. SystemZ: Some of the allocation orders are omitting R12 aliases without explanation. I don't understand this target well enough to fix that. It looks like all the boilerplate could be removed by reserving the right registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132781 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsRegisterInfo.cpp')
-rw-r--r--lib/Target/Mips/MipsRegisterInfo.cpp2
1 files changed, 2 insertions, 0 deletions
diff --git a/lib/Target/Mips/MipsRegisterInfo.cpp b/lib/Target/Mips/MipsRegisterInfo.cpp
index f3f7272..b0984af 100644
--- a/lib/Target/Mips/MipsRegisterInfo.cpp
+++ b/lib/Target/Mips/MipsRegisterInfo.cpp
@@ -127,6 +127,8 @@ getReservedRegs(const MachineFunction &MF) const {
Reserved.set(Mips::SP);
Reserved.set(Mips::FP);
Reserved.set(Mips::RA);
+ Reserved.set(Mips::F31);
+ Reserved.set(Mips::D15);
// SRV4 requires that odd register can't be used.
if (!Subtarget.isSingleFloat() && !Subtarget.isMips32())